MFR50SFTDPN82R5 datasheet, PDF

Datasheet> All Categories > Passive components> The resistor> MFR50SFTDPN82R5

MFR50SFTDPN82R5: DescriptionFixed Resistor, Metal Film, 0.5W, 82.5ohm, 300V, 1% +/-Tol, -25,25ppm/Cel,; CategoryPassive components The resistor; ManufacturerYAGEO; Websitehttp://www.yageo.com/; Environmental Compliance

Download Datasheet Parametric View All

MFR50SFTDPN82R5 Overview

Fixed Resistor, Metal Film, 0.5W, 82.5ohm, 300V, 1% +/-Tol, -25,25ppm/Cel,

MFR50SFTDPN82R5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	886668508
Reach Compliance Code	compliant
Country Of Origin	Mainland China
ECCN code	EAR99
YTEOL	6.95
structure	Cylindrical
JESD-609 code	e3
Lead diameter	0.55 mm
Number of terminals	2
Maximum operating temperature	155 °C
Minimum operating temperature	-55 °C
Package diameter	2.4 mm
Package length	6.3 mm
Package shape	CYLINDRICAL PACKAGE
Package form	Axial
method of packing	Ammo Pack
Rated power dissipation(P)	0.5 W
resistance	82.5 Ω
Resistor type	FIXED RESISTOR
series	MFR
technology	METAL FILM
Temperature Coefficient	25 ppm/°C
Terminal surface	Matte Tin (Sn)
Tolerance	1%
Operating Voltage	300 V

Preview

Download Datasheet

View All

Leaded ResistoRs

Metal Film Resistors

General Type

Normal & Miniature Style [ MFR Series ]

FeatURes

Power Rating

Resistance Tolerance

T.C.R.

1/6W, 1/4W, 1/2W, 1W, 2W, 3W

±0.5%, ±1%, ±5%

±15ppm/°C, ±25ppm/°C, ±50ppm/°C, ±100ppm/°C

deRatiNG CURVe

iNtRodUCtioN

The MFR Series Metal Film Resistors are

manufactured using a vacuum sputtering system

to deposit multiple layers of mixed metal

alloys and passivative materials onto a carefully

treated high grade ceramic substrate. After a

helical groove has been cut in the resistive layer,

tinned connecting leads of electrolytic copper

are welded to the end-caps. The resistors are

coated with layers of blue color lacquer.

For resistors operated in ambient temperatures above 70°C, power rating must be derated

in accordance with the curve below.

Rated Load (%)

100

100 120 140 160

155 °C

Ambient Temperature (°C)

diMeNsioNs

stYLe

Normal

MFR-12

ød

øD

MFR-25

MFR-50

MFR100

MFR200

Miniature

MFR25S

MFR50S

MFR1WS

MFR2WS

MFR3WS

diMeNsioN

3.4±0.3

6.3±0.5

9.0±0.5

11.5±1.0

15.5±1.0

ød

1.9±0.2

2.4±0.2

3.3±0.3

4.5±0.5

5.0±0.5

28±2.0

26±2.0

35±2.0

33±2.0

Unit: mm

ød

0.45±0.05

0.55±0.05

0.8±0.05

Recommended Resources

Voltage-controlled voltage source second-order band-pass filter circuit

SC3071X touch step dimming light circuit

AC non-contact automatic voltage regulator circuit diagram

Video recorder RF converter circuit

Adjustable relay delay switching circuit

845ddr computer motherboard circuit diagram_58

Research on A-type digital flaw detection system based on FPGA.pdf: Research on A-type digital flaw detection system based on FPGA.pdf...; zxopenljx EE_FPGA Learning Park

Phase loss detection of three-phase three-wire circuit: [i=s] This post was last edited by New Electrician Seeking Guidance on 2020-4-1 14:10[/i]I am going to make a soft start switch for a three-phase circuit recently, which needs to realize the phase los...; 电工新手求指导 Analog electronics

EEWORLD University Hall----Principle and Operation of DC Bridge Fudan University: DC Bridge Principle and Operation Fudan University : https://training.eeworld.com.cn/course/5358DC Bridge Principle and Operation Fudan University...; 抛砖引玉 Test/Measurement

Small base stations can also take the center stage in the 5G era: Most people are familiar with base stations (traditional macro base stations). From 2G to 4G, the communication networks we use in our daily lives rely on these traditional macro base stations to comp...; zqy1111 RF/Wirelessly

What is the packaging of integrated circuits? What are the common types of packaging? What are their respective characteristics?: [b][font=宋体][size=4] [/size][/font][/b][b][font=宋体][size=5][color=#0000ff]1. What is the package of integrated circuits? [/color][/size][/font][/b][font=宋体][size=4] [/size][/font] [align=left][color=r...; tiankai001 PCB Design

Vivado prompts [Synth 8-91] ambiguous clock in event control Problem Cause: Comprehensive prompt [Synth 8-91] ambiguous clock in event control. Later it was found that the reason was because the if was written in the always and the else was omitted....; littleshrimp FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components