SIT5156ACCFA025IB-19.123456 datasheet, PDF

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SIT5156ACCFA025IB-19.123456: DescriptionClipped Sine Output Oscillator, 19.123456MHz Nom, CQFN, 10 PIN; CategoryPassive components oscillator; File Size2MB，38 Pages; ManufacturerSiTime; Environmental Compliance

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SIT5156ACCFA025IB-19.123456 Overview

Clipped Sine Output Oscillator, 19.123456MHz Nom, CQFN, 10 PIN

SIT5156ACCFA025IB-19.123456 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145156855680
package instruction	LCC10,.12X.2,53/47/43
Reach Compliance Code	unknown
Other features	ENABLE/DISABLE FUNCTION
Ageing	1 PPM/YEAR
Frequency Adjustment - Mechanical	NO
frequency stability	1%
Installation features	SURFACE MOUNT
Number of terminals	10
Nominal operating frequency	19.123456 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Oscillator type	CLIPPED SINE
Output impedance	10000 Ω
Output level	0.8 V
Package body material	CERAMIC
Encapsulate equivalent code	LCC10,.12X.2,58/52/48
physical size	5.15mm x 3.35mm x 1.06mm
Filter level	MIL-STD-883F
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES

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SiT5156

Description

1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO

Features



The

SiT5156

is a ±0.5 ppm to ±2.5 ppm MEMS Super-

TCXO that is engineered for best dynamic performance. It

is ideal for high reliability telecom, wireless and networking,

industrial, precision GNSS and audio/video applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5156 delivers the best dynamic performance for timing

stability in the presence of environmental stressors such as

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5156 offers three device configurations that can be

ordered using

Ordering Codes

for:



Any frequency from 1 MHz to 60 MHz in 1 Hz steps

Factory programmable options for short lead times

Best dynamic stability under airflow, thermal shock



±0.5 ppm stability across temperature



±15 ppb/

°C

typical

frequency slope (ΔF/ΔT)

-40°C to +105°C operating temperature

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I



Digital control of output frequency and pull range



Up to

±3200

ppm pull range



Frequency pull resolution down to 5 ppt

2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications



The SiT5156 can be factory programmed for any

combination of frequency, stability, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.



Precision GNSS systems

Microwave backhaul

Network routers and switches

Professional audio and video equipment

Storage and servers

Test and measurement

Block Diagram

5.0 mm x 3.2 mm Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5156 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 1.06

May 23, 2020

www.sitime.com

SiT5156

1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO

TABLE OF CONTENTS

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ............................................................................................................................................. 9

Pin-out Top Views................................................................................................................................................................. 9

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10

Waveforms................................................................................................................................................................................. 12

Timing Diagrams ........................................................................................................................................................................ 13

Typical Performance Plots ......................................................................................................................................................... 14

Architecture Overview ................................................................................................................................................................ 16

Frequency Stability ............................................................................................................................................................. 16

Output Frequency and Format............................................................................................................................................ 16

Output Frequency Tuning ................................................................................................................................................... 16

Pin 1 Configuration (OE, VC, or NC)

.................................................................................................................................. 17

Device Configurations ................................................................................................................................................................ 17

TCXO Configuration ........................................................................................................................................................... 17

VCTCXO Configuration ...................................................................................................................................................... 18

DCTCXO Configuration ...................................................................................................................................................... 19

VCTCXO-Specific Design Considerations ................................................................................................................................. 20

Linearity .............................................................................................................................................................................. 20

Control Voltage Bandwidth ................................................................................................................................................. 20

FV Characteristic Slope K

................................................................................................................................................. 20

Pull Range, Absolute Pull Range ........................................................................................................................................ 21

DCTCXO-Specific Design Considerations ................................................................................................................................. 22

Pull Range and Average Pull Range .................................................................................................................................. 22

Output Frequency ............................................................................................................................................................... 23

C Control Registers .......................................................................................................................................................... 25

Register Descriptions.......................................................................................................................................................... 25

............................................................ 25

OE Control, Digital Frequency Control Most Significant Word (MSW)

......................................... 26

[15]

....................................................................................... 27

Serial Interface Configuration Description .......................................................................................................................... 28

Serial Signal Format ........................................................................................................................................................... 28

Parallel Signal Format ........................................................................................................................................................ 29

Parallel Data Format ........................................................................................................................................................... 29

C Timing Specification ...................................................................................................................................................... 31

C Device Address Modes ................................................................................................................................................. 32

Schematic Example ............................................................................................................................................................ 33

Dimensions and Patterns ........................................................................................................................................................... 34

Layout Guidelines ...................................................................................................................................................................... 35

Manufacturing Guidelines .......................................................................................................................................................... 35

Additional Information ................................................................................................................................................................ 36

Revision History ......................................................................................................................................................................... 37

Rev 1.06

Page 3 of 38

www.sitime.com

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