C1632C471K1RAC datasheet, PDF - EEWORLD Datasheet

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C1632C471K1RAC: DescriptionISOLATED C NETWORK, 100V, X7R, 0.00047uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT; CategoryPassive components capacitor; File Size777KB，2 Pages; ManufacturerKEMET; Websitehttp://www.kemet.com; Environmental Compliance

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C1632C471K1RAC Overview

ISOLATED C NETWORK, 100V, X7R, 0.00047uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT

C1632C471K1RAC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1767260711
package instruction	CHIP,
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	8.72
capacitance	0.00047 µF
Capacitor type	ARRAY/NETWORK CAPACITOR
JESD-609 code	e3
length	3.2 mm
Installation features	SURFACE MOUNT
negative tolerance	10%
Network Type	ISOLATED C NETWORK
Number of components	1
Number of functions	4
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
encapsulated code	CHIP
Package shape	RECTANGULAR PACKAGE
method of packing	BULK
positive tolerance	10%
Rated (DC) voltage (URdc)	100 V
Maximum seat height	1.35 mm
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
Terminal surface	Matte Tin (Sn)
Terminal pitch	0.8 mm
Terminal shape	WRAPAROUND
width	1.6 mm

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CERAMIC CAPACITOR ARRAY

FEATURES

•

Four individual capacitors inside

one 1206 monolithic structure

Saves board and inventory space

One placement instead of four - less costly

•

Easier to handle and solder than 4 smaller chips

Tape and reel per EIA 481-1

RoHS Compliant

CAPACITOR OUTLINE DRAWING

P/2

Ref

BW1

TABLE 1

EIA DIMENSIONS – MILLIMETERS (INCHES)

Size

Code

1632

Length

3.2 (0.126)

0.2 (0.008)

Width

1.6 (.063)

0.2 (.008)

Thickness

T (max.)

0.7 - 1.35

(0.027 - 0.053)

Bandwidth

BW1

Pitch

0.40 (0.016)

0.1 - 0.5

0.8 (0.031)

0.2 (0.008) (0.004 - 0.020)

0.1 (0.004)

Notes:

1. Metric is controlling - English for reference only.

2. Pitch (P) tolerances are non-cumulative along the package.

3. Thickness (T) depends on capacitance.

CERAMIC ARRAY ORDERING INFORMATION

1632

103

END METALLIZATION

C-Standard

(Tin-plated nickel barrier)

FAILURE RATE LEVEL

A- Not Applicable

TEMPERATURE CHARACTERISTIC

Designated by Capacitance

Change Over T

emperature Range

G – C0G (NP0) (±30 PPM/°C)

R – X7R (±15%)

VOLTAGE

5 = 50v; 3 = 25v; 4 = 16v; 8=10v

CERAMIC

EIA SIZE CODE

Ceramic chip array

SPECIFICATION

C - Standard

CAPACITANCE CODE

Expressed in Picofarads (pF)

First two digits represent significant figures.

Third digit specifies number of zeros. (Use 9

for 1.0 thru 9.9pF (Example: 2.2pF = 229

CAPACITANCE TOLERANCE

K –

±10%:

M –

±20%

Standard Tolerances

Contact factory for any special requirements.

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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