Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using
’trench’
technology
the device features very low on-state
resistance and has integral zener
diodes giving ESD protection. It is
intended for use in automotive and
general
purpose
switching
applications.
BUK7840-55
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 10 V
MAX.
55
10.7
1.8
150
40
UNIT
V
A
W
˚C
mΩ
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g
s
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
D
I
DM
P
tot
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
sp
= 25 ˚C
On PCB in Fig.19
T
amb
= 25 ˚C
On PCB in Fig.19
T
amb
= 100 ˚C
T
sp
= 25 ˚C
T
sp
= 25 ˚C
On PCB in Fig.19
T
amb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
16
10.7
5
3.1
40
10.7
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
January 1998
1
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
THERMAL RESISTANCES
SYMBOL
R
th j-sp
R
th j-amb
PARAMETER
From junction to solder point
From junction to ambient
CONDITIONS
Mounted on any PCB
Mounted on PCB of Fig.18
TYP.
12
-
BUK7840-55
MAX.
15
70
UNIT
K/W
K/W
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 150˚C
T
j
= -55˚C
V
DS
= 55 V; V
GS
= 0 V;
V
GS
=
±10
V
T
j
= 150˚C
T
j
= 150˚C
T
j
= 150˚C
MIN.
55
50
2.0
1.2
-
-
-
-
-
16
-
-
TYP.
-
-
3.0
-
-
0.05
-
0.04
-
-
30
-
MAX.
-
-
4.0
-
4.4
10
100
1
10
-
40
74
UNIT
V
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
Gate source breakdown voltage I
G
=
±1
mA
Drain-source on-state
V
GS
= 10 V; I
D
= 5 A
resistance
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
CONDITIONS
V
DS
= 25 V; I
D
= 5 A; T
j
= 25˚C
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
3
-
-
-
-
-
-
-
TYP.
12
700
200
100
15
50
33
20
MAX.
-
880
240
140
23
75
50
30
UNIT
S
pF
pF
pF
ns
ns
ns
ns
V
DD
= 30 V; I
D
= 9 A;
V
GS
= 10 V; R
g
= 10
Ω
T
j
= 25˚C
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= -55 to 175˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
T
sp
= 25˚C
T
sp
= 25˚C
I
F
= 5 A; V
GS
= 0 V
I
F
= 5 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
MIN.
-
-
-
-
-
TYP.
-
-
0.85
45
0.3
MAX.
10.7
40
1.1
-
-
UNIT
A
A
V
ns
µC
January 1998
2
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 3.6 A; V
DD
≤
25 V;
V
GS
= 10 V; R
GS
= 50
Ω;
T
sp
= 25 ˚C
MIN.
-
TYP.
-
BUK7840-55
MAX.
60
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
BUKX840-55
100
ID/A
RDS(ON) = VDS/ID
10
tp =
1 us
10 us
100 us
1 ms
DC
1
10 ms
100 ms
0
20
40
60
80
100
Tmb / C
120
140
0.1
0.1
1
VDS/V
10
55
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
sp
)
Fig.3. Safe operating area. T
sp
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
1E+02
3E+01
1E+01
3E+00
1E+00
3E-01
1E-01
3E-02
Zth / (K/W)
BUK9840-55
0.5
0.2
0.1
0.05
0.02
P
D
t
p
p
D= t
T
T
0
1E-05
1E-03
t/s
1E-01
t
0
20
40
60
80
Tmb / C
100
120
140
1E-02
1E-07
1E+01
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
sp
); conditions: V
GS
≥
10 V
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
January 1998
3
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
BUK7840-55
20
ID/A
16
8.0
6.5
VGS/V =
6.0
16
gfs/S
14
12
15
10
5.5
10
8
6
4
10
5.0
5
4.5
4.0
2
0
0
2
4
6
8
10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ID/A
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
VGS/V =
70
6
60
50
40
30
20
10
0
0
5
10
15
20
25
6.5
7
8
10
5.5
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
80
2.5
a
BUK98XX-55
Rds(on) normalised to 25degC
2
1.5
1
0.5
-100
-50
0
ID/A
50
Tmb / degC
100
150
200
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
20
ID/A
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 5 A; V
GS
= 10 V
VGS(TO) / V
max.
BUK78xx-55
5
15
4
typ.
3
10
Tj/C =
5
150
25
min.
2
1
0
0
-100
0
1
2
3 VGS/V 4
5
6
7
-50
0
50
Tj / C
100
150
200
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
January 1998
4
Rev 1.000
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
BUK7840-55
1E-01
Sub-Threshold Conduction
20
IF/A
1E-02
2%
typ
98%
15
Tj/C =
150
25
1E-03
10
1E-04
5
1E-05
0
1E-06
0
1
2
3
4
5
0
0.2
0.4
0.6
0.8
VSDS/V
1
1.2
1.4
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
1.4
1.2
1.0
0.8
Ciss
0.6
0.4
0.2
Coss
Crss
0
0.01
0.1
1
VDS/V
10
100
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
Thousands pF
20
40
60
80
100
Tmb / C
120
140
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
12
VGS/V
10
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
sp
); conditions: I
D
= 3.6 A
+
L
VDS
VDS = 14V
VDS = 44V
VDD
8
6
VGS
0
RGS
T.U.T.
-
-ID/100
4
2
R 01
shunt
0
0
5
10
QG/NC
15
20
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 9 A; parameter V
DS
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
January 1998
5
Rev 1.000
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