Ordering Information .................................................................................................................................................................... 2
Dimensions and Patterns ― 3.2 x 2.5 mm................................................................................................................................. 13
Dimensions and Patterns ― 5.0 x 3.2 mm................................................................................................................................. 13
Dimensions and Patterns ― 7.0 x 5.0 mm................................................................................................................................. 14
Additional Information ................................................................................................................................................................ 15
Revision History ......................................................................................................................................................................... 16
Rev 1.01
Page 2 of 18
www.sitime.com
SiT3342
1 MHz to 220 MHz Ultra-low Jitter, Endura™ Series Differential VCXO
Electrical Characteristics
Table 2. Electrical Characteristics – Common to LVPECL, LVDS and HCSL
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with standard
output termination shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-15
-25
-35
-50
Operating Temperature Range
T_use
-20
-40
-40
-40
Acceleration (g) sensitivity,
Gamma Vector
Supply Voltage
F_g
–
Typ.
–
–
–
–
–
–
–
–
–
–
Max.
220
+15
+25
+35
+50
+70
+85
+95
+105
0.1
Unit
MHz
ppm
ppm
ppm
ppm
°C
°C
°C
°C
ppb/g
Extended Industrial
Low sensitivity grade; total gamma over 3 axes; 15 Hz to 2 kHz;
MIL-PRF-55310, computed per section 4.8.18.3.1
Extended Commercial
Industrial
Condition
Accurate to 6 decimal places
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, load variations, and first year aging at 25°C,
with VIN voltage at Vdd/2.
±15
ppm is only guaranteed for pull range up to
±100
ppm.
Frequency Range
Frequency Stability
Temperature Range
Rugged Characteristics
Supply Voltage
Vdd
2.97
2.7
2.52
2.25
Pull Range
PR
3.3
3.0
2.8
2.5
3.63
3.3
3.08
2.75
V
V
V
V
ppm
See the APR (Absolute Pull Range)
Table 11.
Contact SiTime
for custom pull range options
Voltage at which maximum frequency deviation is guaranteed
Voltage at which minimum frequency deviation is guaranteed
Contact SiTime
for other input bandwidth options
Voltage Control Characteristics
±25, ±50, ±80, ±100, ±150,
±200, ±400, ±800, ±1600,
±3200
90%
–
–
–
–
–
–
10
10
–
–
10%
–
–
1.0
–
Input Characteristics
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Duty Cycle
Startup Time
OE Enable/Disable Time
VIH
VIL
Z_in
DC
T_start
T_oe
70%
–
–
45
–
–
–
–
100
–
–
–
–
30%
-
55
3.0
3.8
Vdd
Vdd
kΩ
%
ms
µs
Measured from the time Vdd reaches its rated minimum value
f = 156.25 MHz. Measured from the time OE pin reaches
rated VIH and VIL to the time clock pins reach 90% of swing
and high-Z. See
Figure 9
and
Figure 10
Pin 2, OE
Pin 2, OE
Pin 2, OE logic high or logic low
Upper Control Voltage
Lower Control Voltage
Control Voltage Input Impedance
Control Voltage Input Bandwidth
Pull Range Linearity
Frequency Change Polarity
VC_U
VC_L
VC_z
V_c
Lin
–
Vdd
Vdd
MΩ
kHz
%
Positive Slope
Output Characteristics
Startup and OE Timing
Rev 1.01
Page 3 of 18
www.sitime.com
SiT3342
1 MHz to 220 MHz Ultra-low Jitter, Endura™ Series Differential VCXO
Table 3. Electrical Characteristics – LVPECL Specific
Parameter
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
RMS Period Jitter
[4]
RMS Phase Jitter (random)
Symbol
Idd
I_OE
I_leak
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_jitt
T_phj
Min.
–
–
–
–
Vdd-1.15
Vdd-2.0
1.2
–
–
–
Typ.
78
53
0.15
–
–
–
1.6
225
1.0
0.225
Max.
92
61
–
33
Vdd-0.7
Vdd-1.5
2.0
290
1.6
0.270
Unit
mA
mA
A
mA
V
V
V
ps
ps
ps
Condition
Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V
OE = Low
OE = Low
Maximum average current drawn from OUT+ or OUT-
See
Figure 5
See
Figure 5
See
Figure 6
20% to 80%, see
Figure 6
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -20 to 70°C and -40 to 85°C
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -40 to 95°C and -40 to 105°C
f = 156.25 MHz, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, includes spurs, all Vdd
levels
f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -20 to 70°C and -40 to 85°C
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdd levels, includes spurs, pull range =
±100
ppm. Temperature
ranges -40 to 95°C and -40 to 105°C
f = 156.25 MHz, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, includes spurs, all Vdd
Recently, a 5A USB port was loose, so I fixed it based on the idea that electronic engineers should do more hands-on work (poor, no money, can't bear to throw it away). The effect is quite satisfactor...
When using CC2640R2F, I found that some projects in the lower version of SDK are no longer available in the higher version of SDK, for example:
There is multi_role in simplelink_cc2640r2_sdk_1_40_00_4...
The first company on the Internet to support the use of buildroot 2021 to build the Allwinner RISC-V 64 architecture Nezha D1 development boardPengfeng Technology's RVBoards-Nezha "The first Debian/Li...
[align=left][color=rgb(25, 25, 25)][font="]Operation timing is always the most important content of using any IC chip. If you understand the timing diagram, it will be very easy to operate the chip. A...
Efficiently complete chip-level signoff convergence, accelerate chip generation and time to market
Cadence Certus Closure Solution is the industry's first fully automated, large-scale distributed envi...
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
