CTS1275X0063B0P datasheet, PDF

CTS1275X0063B0P: DescriptionCAPACITOR, TANTALUM, SOLID, 63 V, 2.7 uF, THROUGH HOLE MOUNT, AXIAL LEADED; CategoryPassive components capacitor; File Size169KB，19 Pages; ManufacturerVishay; Websitehttp://www.vishay.com

Download Datasheet Parametric View All

CTS1275X0063B0P Overview

CAPACITOR, TANTALUM, SOLID, 63 V, 2.7 uF, THROUGH HOLE MOUNT, AXIAL LEADED

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	2130657241
package instruction	,
Reach Compliance Code	unknown
Country Of Origin	Israel
ECCN code	EAR99
YTEOL	4.94
capacitance	2.7 µF
Capacitor type	TANTALUM CAPACITOR
diameter	4.9 mm
dielectric materials	TANTALUM (DRY/SOLID)
JESD-609 code	e0
leakage current	0.0017 mA
length	12.04 mm
Installation features	THROUGH HOLE MOUNT
negative tolerance	20%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package shape	TUBULAR PACKAGE
Package form	Axial
method of packing	TR
polarity	POLARIZED
positive tolerance	20%
Rated (DC) voltage (URdc)	63 V
surface mount	NO
Delta tangent	0.06
Terminal surface	Tin/Lead (Sn/Pb)
Terminal shape	WIRE

Demystifying low Iq: How to design near 100% duty cycle for ultra-low power applications using WEBENCH: Many battery-powered applications require a buck converter to operate at 100% duty cycle, where V IN is close to V OUT , to extend battery life when the battery voltage reaches its minimum value. For ...; alan000345 TI Technology Forum

Graduation project needs advice: I am a senior in college. I don't know what to do for my graduation project in communication engineering. I would like some advice from an expert....; ZF追风 DIY/Open Source Hardware

HDMI application market has broad prospects: High-Definition Multimedia Interface (HDMI) has become a widely used interface standard for digital televisions and consumer electronics products, bringing high-quality experience to home entertainmen...; rain MCU

Please tell me how to use logic circuit to generate such timing: As shown in the figure below, A and B are inputs, and C is output. After B generates a high level, C outputs a high level at the rising edge of A. C outputs a low level at the rising edge of B. If B m...; littleshrimp FPGA/CPLD

TPS5430 12V input 5V output is too low: [i=s]This post was last edited by liunixy on 2019-6-5 19:23[/i]As shown in the figure above, the input is 12V and the designed output is 5V, but the actual output voltage is only about 3V when no load...; liunixy Power technology

my country's blog users are expected to reach nearly 100 million next year: my country's blog users are expected to reach nearly 100 million next year 2006-7-17With the increase in the number of Chinese netizens and the further popularization of blogs, the number of Chinese b...; hkn RF/Wirelessly

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components