xr
FEBRUARY 2005
PRELIMINARY
XRK4991A
REV. P1.0.2
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
at the clock destination. This feature minimizes clock
distribution difficulty while allowing maximum system
clock speed and flexibility.
FEATURES
FUNCTIONAL DESCRIPTION
The XRK4991A 3.3V High-Speed Low-Voltage
Programmable Skew Clock Buffer offers user
selectable control over system clock functions to
optimize the timing of high-performance computer
systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified
output skews and full-swing logic levels (LVTTL).
Each output can be hardwired to one of nine delay or
function configurations. Delay increments of 0.7 to
1.5 ns are determined by the operating frequency
with outputs able to skew up to
±6
time units from
their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission
line delay effects to be canceled. When this “zero
delay” capability is combined with the selectable
output skew functions, the user can create output-to-
output delays of up to
±12
time units.
Divide-by-two and divide-by-four output functions are
provided for additional flexibility in designing complex
clock systems. When combined with the internal PLL,
these divide functions allow distribution of a low-
frequency clock that can be multiplied by two or four
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRK4991A
TEST
PE
FB_IN
PHASE
CLKIN
FSEL
SELD0
SELD1
Select Inputs
SELC0
SELC1
SELB0
SELB1
SELA0
SELA1
FREQ
DET
FILTER
•
Ref input is 5V tolerant
•
3 pairs of programmable skew outputs
•
Low skew: 200ps same pair, 250ps all outputs
•
Selectable
positive
or
negative
edge
synchronization: Excellent for DSP applications
•
Synchronous output enable
•
Output frequency: 3.75MHz to 85MHz
•
2x, 4x, 1/2, and 1/4 outputs
•
2 skew grades
•
3-level inputs for skew and PLL range control
•
PLL bypass for DC testing
•
External feedback, internal loop filter
•
12mA balanced drive outputs
•
32-pin PLCC package
•
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
•
Green packaging
VCO AND TIME
UNIT GENERATOR
0E
QD0
QD1
SKEW
SELECT
QC0
QC1
QB0
MATRIX
QB1
QA0
QA1
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
xr
REV. P1.0.2
PRODUCT ORDERING INFORMATION
P
RODUCT
N
UMBER
XRK4991AIJ-5
XRK4991ACJ-5
XRK4991ACJ-7
XRK4991AIJ-7
A
CCURACY
500 ps
500 ps
750 ps
750 ps
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
F
IGURE
2. P
IN
O
UT OF THE
XRK4991
SELC0
4
SELC1
SELD0
SELD1
PE
V
CCN
QD1
QDO
GND
GND
5
6
7
8
9
10
11
12
13
14
QD1
3
2
1
32
31
SELB1
30
29
28
27
26
SELB0
OE
SELA1
1F0
V
CCN
QA0
QA1
GND
GND
25
24
23
22
21
20
QB0
CLKIN
XRK4991A
15
QC0
16
V
CCN
17
FB_IN
18
V
CCN
2
QB1
TEST
19
FSEL
GND
V
CCQ
xr
REV. P1.0.2
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
PRELIMINARY
PIN DESCRIPTIONS
P
IN
N
AME
CLKIN
FB_IN
FSEL
SELA0
SELA1
SELB0
SELB1
SELC0
SELC1
SELD0
SELD1
TEST
OE
P
IN
#
1
17
3
26
27
29
30
4
5
7
1
31
28
T
YPE
I
I
I
I
I
I
I
I
I
D
ESCRIPTION
Reference frequency input. This input supplies the frequency and timing against
which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs).
Three-level frequency range select. Set Table 2.
Three-level function selects inputs for output pair 1 (QA0, QA0]). Table 3.
Three-level function selects inputs for output pair 2 (QB0, QB1). Table 3.
Three-level function selects inputs for output pair 3 (QC0, QC1). See Table 3.
Three-level function selects inputs for output pair 4 (QD0, QD1). See Table 3.
Three-level select. See test mode section under the block diagram descriptions.
Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0])
in a "Low" state - QC[1:0] may be used as the feedback signal to maintain phase
lock. When TEST is held at MID level and OE is "High", the nF[1:0] pins act as
output disable controls for individual banks when nF[1:0] = LL. Set OE "Low" for
normal operation.
Selectable positive or negative edge control. When "Low"/"High" the outputs are
synchronized with the negative/positive edge of the reference clock.
Output pair 1. See Table 2.
Output pair 2. See Table 2.
Output pair 3. See Table 2.
Output pair 4. See Table 2.
Power supply for output drivers.
PE
QA0
QA1
QB0
QB1
QC0
QC1
QD0
QD1
V
CCN
8
24
23
20
19
15
14
11
10
9
16
18
25
2
12
13
21
22
32
I
O
O
O
O
PWR
V
CCQ
GND
PWR
PWR
Power supply for internal circuitry.
Ground.
3
XRK4991A
PRELIMINARY
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
EXTERNAL FEEDBACK
xr
REV. P1.0.2
By providing external feedback, the XRK4991A gives users flexibility with regard to skew adjustment. The
FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO to adjust upwards or downwards accordingly. An internal loop filter moderates the
response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide
minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
T
ABLE
1: PLL P
ROGRAMMABLE
S
KEW
R
ANGE AND
R
ESOLUTION
T
ABLE
FSEL = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
1/(44 x F
NOM
)
15 to 35MHz
FSEL = MID
1/(26 x F
NOM
)
25 to 60MHz
FSEL = HIGH
1/(16 x F
NOM
)
40 to 100MHz
C
OMMENTS
+9.09ns
+49°
+14%
+9.23ns
+83°
+23%
+9.38ns
+135°
+37%
ns
Phase Degrees
% of Cycle Time
Example 1, F
NOM
= 15MHz
Example 2, F
NOM
= 25MHz
Example 3, F
NOM
= 30MHz
Example 4, F
NOM
= 40MHz
Example 5, F
NOM
= 50MHz
Example 6, F
NOM
= 80MHz
N
OTES
:
1.
t
U
= 1.52ns
t
U
= 0.91ns
t
U
= 0.76ns
t
U
= 1.54ns
t
U
= 1.28ns
t
U
= 0.96ns
t
U
= 0.77ns
t
U
= 1.56ns
t
U
= 1.25ns
t
U
= 0.78ns
The device may be operated outside recommended frequency ranges without damage, but functional operation is
not guaranteed. Selecting the appropriate FSEL value based on input frequency range allows the PLL to operate
in its ‘sweet spot’ where jitter is lowest.
The level to be set on FSEL is determined by the nominal operating frequency of the VCO and Time Unit
Generator. The VCO frequency always appears at QA[1:0], QB[1:0] and the higher outputs when they are
operated in their undivided modes. The frequency appearing at the CLKIN and FB_IN inputs will be the same as
the VCO when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be
1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output
as the FB_IN input.
Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for
feedback, then adjustment range will be greater. For example if a 4t
U
skewed output is used for feedback, all other
outputs will be skewed –4t
U
in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’
range applies to output pairs 3 and 4 where ± 6t
U
skew adjustment is possible and at the lowest FNOM value.
2.
3.
4
xr
REV. P1.0.2
XRK4991A
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
T
ABLE
2: F
REQUENCY
R
ANGE
S
ELECT AND
t
U
C
ALCULATION
[1]
f
NOM
(MH
Z
)
t
U
= 1 /
f
NOM X
N
M
AX
30
50
85
WHERE
PRELIMINARY
A
PPROXIMATE
F
REQUENCY
(MH
Z
)
AT
WHICH
t
U
FSEL
[2,3]
LOW
MID
HIGH
M
IN
15
25
40
N=
= 1.0ns
44
26
16
22.7
38.5
62.5
SKEW SELECT MATRIX
The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout
drivers (Qx[0:1]), and two corresponding three-level function select (SELx[0:1]) inputs. Table 2 below shows
the nine possible output functions for each section as determined by the function select inputs. All times are
measured with respect to the CLKIN input assuming that the output connected to the FB_IN input has 0t
U
selected.
T
ABLE
3: P
ROGRAMMABLE
S
KEW
C
ONFIGURATIONS
[1]
F
UNCTION
S
ELECTS
SEL
X
1
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
SEL
X
0
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
QA[1:0], QB[1:0]
-4t
U
-3t
U
-2t
U
-1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
O
UTPUT
F
UNCTIONS
QC[1:0]
Divide by 2
-6t
U
-4t
U
-2t
U
0t
U
+2t
U
+4t
U
+6t
U
Divide by 4
QD[1:0]
Divide by 2
-6t
U
-4t
U
-2t
U
0t
U
+2t
U
+4t
U
+6t
U
Inverted
N
OTES
:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID
indicates an open connection. Internal termination circuitry holds an unconnected input to V
CC
/2.
2.
The level to be set on FSEL is determined by the “normal” operating frequency (f
NOM
) of the V
CO
and Time Unit
Generator (see Logic Block Diagram). Nominal frequency (f
NOM
) always appears at QA0 and the other outputs
when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN
inputs will be f
NOM
when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN
inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency multiplication by using a divided output
as the FB_IN input.
When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until V
CC
has reached
2.8V.
3.
5
京公网安备 11010802033920号
EEWORLD
