Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 30
Ω
series
74LVC162245A;
termination resistors; 5 V tolerant input/output; 3-state 74LVCH162245A
FEATURES
•
5 V tolerant inputs/outputs for interfacing with 5 V logic
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
MULTIBYTE
TM
flow-through standard pin-out
architecture
•
Low inductance multiple power and ground pins for
minimum noise and ground bounce
•
Direct interface with TTL levels
•
Inputs accept voltages up to 5.5 V
•
Integrated 30
Ω
termination resistors
•
High-impedance when V
CC
= 0 V
•
All data inputs have bushold (74LVCH162245A only)
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
DESCRIPTION
The 74LVC(H)162245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. These features
allow the use of these devices as translators in a mixed
3.3 and 5 V environment.
The 74LVC(H)162245A is a 16-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions.
The 74LVC(H)162245A features two output enable (nOE)
inputs for easy cascading and two send/receive (nDIR)
inputs for direction control. nOE controls the outputs so
that the buses are effectively isolated. This device can be
used as two 8-bit transceivers or one 16-bit transceiver.
The 74LVCH162245A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
The 74LVC(H)162245A is designed with 30
Ω
series
termination resistors in both HIGH and LOW output stages
to reduce line noise.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
I/O
C
PD
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
PARAMETER
propagation delay nAn to nBn; nBn to nAn
input capacitance
input/output capacitance
power dissipation capacitance
V
CC
= 3.3 V; notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
TYPICAL
3.3
5.0
10
28
ns
pF
pF
pF
UNIT
2003 Dec 08
2
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