PKL24A128ATFMCCC(R) datasheet, PDF

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PKL24A128ATFMCCC(R): DescriptionKL24/KL25 Product Brief; File Size283KB，21 Pages; ManufacturerFREESCALE (NXP)

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KL24/KL25 Product Brief

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Freescale Semiconductor

Product Brief

Document Number:KL25PB

Rev. 2, 6/2012

Supports all KL24 and KL25 devices

KL24/KL25 Product Brief

Contents

1 Kinetis L Series

The Kinetis L series is the most scalable portfolio of ultra low-

power, mixed-signal ARM Cortex-M0+ MCUs in the

industry. The portfolio includes 5 MCU families that offer a

broad range of memory, peripheral and package options.

Kinetis L Series families share common peripherals and pin-

counts allowing developers to migrate easily within an MCU

family or between MCU families to take advantage of more

memory or feature integration. This scalability allows

developers to standardize on the Kinetis L Series for their end

product platforms, maximising hardware and software reuse

and reducing time-to-market.

Features common to all Kinetis L series families include:

• 48 MHz ARM Cortex-M0+ core

• High-speed 12/16-bit analog-to-digital converters

• 12-bit digital-to-analog converters for all series except

for KLx4 family

• High-speed analog comparators

• Low-power touch sensing with wake-up on touch from

reduced power states for all series except for KLx4

family

• Powerful timers for a broad range of applications

including motor control

• Low power focused serial communication interfaces

such as low power UART, SPI, I2C etc.

• Single power supply: 1.71V - 3.6V with multiple low-

power modes support single operation temperature: -40

~ 105 °C (exclude CSP package)

Preliminary

General Business Information

Kinetis L Series.........................................................1

KL24/KL25 Sub-Family Introduction......................3

Block Diagram..........................................................3

Features.....................................................................6

Power modes...........................................................18

Revision History.....................................................20

Kinetis L Series

Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad

range of communication, connectivity, and human-machine interface peripherals. Each MCU family is supported by a

market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners. The KL0x family is the

entry-point to the Kinetis L series and is compatible with the 8-bit S08PT family. The KL1x/2x/3x/4x families are compatible

with each other and their equivalent ARM Cortex-M4 Kinetis K series families - K10/20/30/40.

Family

Program

Flash

Packages

64-121pin

32-121pin

32-80pin

16-48pin

Mixed signal

Key Features

KL4x Family

128-256KB

KL3x Family

64-256KB

KL2x Family

32-256KB

KL1x Family

32-256KB

KL0x Family

8-32KB

Low power

USB

Segment LCD

Figure 1. Kinetis L series families of MCU portfolio

All Kinetis L series families include a powerful array of analog, communication and timing and control peripherals with the

level of feature integration increasing with flash memory size and the pin count. Features within the Kinetis L series families

include:

• Core and Architecture:

• ARM Cortex-M0+ Core delivering 1.77 CoreMark/MHz from single-cycle access memories

• Single-cycle access to I/O and critical peripherals: Up to 50 percent faster than standard I/O, improves

reaction time to external events allowing bit banging and software protocol emulation

• Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction and

ISR entry

• Excellent code density vs. 8-bit and 16-bit MCUs - reduces flash size, system cost and power consumption

• Optimized access to program memory: Accesses on alternate cycles reduces power consumption

• 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex-M3/M4: Reuse existing

compilers and debug tools

• Simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging

of 8/16/32-bit data in memory

• Linear 4 GB address space removes the need for paging/banking, reducing software complexity

• ARM third-party ecosystem support: Software and tools to help minimize development time/cost

• Micro Trace Buffer: Lightweight trace solution allows fast bug identification and correction

• BME: Bit manipulation engine reduces code size and cycles for bit oriented operations to peripheral registers

eliminating traditional methods where the core would need to perform read-modify-write instructions.

• Up to 4-channel DMA for peripheral and memory servicing with minimal CPU intervention

• Broad range of performance levels with CPU frequencies up to 48 MHz

• Ultra low-power:

• Next-generation 32-bit ARM Cortex M0+ core: 2x more CoreMark/mA than the closest 8/16-bit architecture

KL24/KL25 Product Brief, Rev. 2, 6/2012

Preliminary

General Business Information

Freescale Semiconductor, Inc.

KL24/KL25 Sub-Family Introduction

•

• Multiple flexible low-power modes, including new operation clocking option which reduces dynamic power by

shutting off bus and system clocks for lowest power core processing. Peripherals with an alternate asynchronous

clock source can continue operation.

• UART, SPI, I2C, ADC, DAC, TPM, LPT and DMA support low-power mode operation without waking up the

core

Memory:

• Scalable memory footprints from 8 KB flash / 1 KB SRAM to 128 KB flash / 16 KB SRAM

• Embedded 64 B cache memory for optimizing bus bandwidth and flash execution performance (feature not

available on KL02 family)

Mixed-signal analog:

• Fast, high precision 16-, or 12-bit ADCs with optional differential pairs, 12-bit DACs, high speed comparators.

Powerful signal conditioning, conversion and analysis capability with reduced system cost

Human Machine Interface (HMI):

• Optional capacitive Touch Sensing Interface with full low-power support and minimal current adder when

enabled

Connectivity and Communications:

• All UARTs support DMA transfers, and can trigger when data on bus is detected, UART0 supports 4x to 32x

over sampling ratio. Asynchronous transmit and receive operation for operating in STOP/VLPS modes.

• Up to two SPIs

• Up to two IICs

• Full-speed USB OTG controller with on-chip transceiver

Reliability, Safety and Security:

• Internal watchdog

Timing and Control:

• Powerful timer modules which support general purpose, PWM, and motor control functions

• Periodic Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and timer

modules

System:

• GPIO with pin interrupt functionality

• Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully

functional flash and analog peripherals

• Ambient operating temperature ranges from -40 °C to 105 °C

The device is highly-integrated, market leading ultra low power 32-bit microcontroller based on the enhanced Cortex-M0+

(CM0+) core platform. The family derivatives feature:

• Core platform clock up to 48 MHz, bus clock up to 24 MHz

• Memory option is up to 128 KB Flash and 16 KB RAM

• Wide operating voltage ranges from 1.71V to 3.6V with full functional Flash program/erase/read operations

• Multiple package options from 32-pin to 80-pin

• Ambient operating temperature ranges from –40 °C to 105 °C

The family acts as an ultra low power, cost effective microcontroller to provide developers an appropriate entry-level 32-bit

solution. The family is next generation MCU solution for low cost, low power, high performance devices applications. It’s

valuable for cost-sensitive, portable applications requiring long battery life-time.

2 KL24/KL25 Sub-Family Introduction

3 Block Diagram

The below figure shows a superset block diagram of the device. Other devices within the family have a subset of the features.

KL24/KL25 Product Brief, Rev. 2, 6/2012

Freescale Semiconductor, Inc.

Preliminary

General Business Information

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