SCAN921226HSM/NOPB datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> SCAN921226HSM/NOPB

SCAN921226HSM/NOPB: DescriptionHigh Temperature 20MHz - 80MHz 10-Bit Deserializer with IEEE 1149.1 Test Access 49-NFBGA -40 to 125; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size1MB，29 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/; Environmental Compliance

Download Datasheet Parametric View All

SCAN921226HSM/NOPB Overview

High Temperature 20MHz - 80MHz 10-Bit Deserializer with IEEE 1149.1 Test Access 49-NFBGA -40 to 125

SCAN921226HSM/NOPB Parametric

Parameter Name	Attribute value
Brand Name	Texas Instruments
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Amphenol
Parts packaging code	BGA
package instruction	GREEN, BGA-49
Contacts	49
Reach Compliance Code	compliant
ECCN code	5A991.B.1
Factory Lead Time	1 week
Is Samacsys	N
Differential output	NO
Input properties	DIFFERENTIAL SCHMITT TRIGGER
Interface integrated circuit type	LINE RECEIVER
Interface standards	IEEE 1149.1
JESD-30 code	S-PBGA-B49
JESD-609 code	e1
length	7 mm
Humidity sensitivity level	4
Number of functions	1
Number of terminals	49
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA49,7X7,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum receive delay
Number of receiver bits	1
Maximum seat height	1.5 mm
Maximum slew rate	120 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
Supply voltage 1-max	3.6 V
Mains voltage 1-minute	3 V
Supply voltage1-Nom	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm
Base Number Matches	1

Preview

Download Datasheet

View All

SCAN921025H, SCAN921226H

www.ti.com

SNLS185C – OCTOBER 2004 – REVISED MAY 2013

SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes

with IEEE 1149.1 (JTAG) and at-speed BIST

Check for Samples:

SCAN921025H, SCAN921226H

FEATURES

High Temperature Operation to 125°C

IEEE 1149.1 (JTAG) Compliant and At-Speed

BIST Test Mode

Clock Recovery from PLL Lock to Random

Data Patterns

Ensured Transition Every Data Transfer Cycle

Chipset (Tx + Rx) Power Consumption < 600

mW (Typ) @ 80 MHz

Single Differential Pair Eliminates Multi-

Channel Skew

800 Mbps Serial Bus LVDS Data Rate (at 80

MHz Clock)

10-bit Parallel Interface for 1 Byte Data Plus 2

Control Bits

Synchronization Mode and LOCK Indicator

Programmable Edge Trigger on Clock

High Impedance on Receiver Inputs When

Power is Off

Bus LVDS Serial Output Rated for 27Ω Load

Small 49-Lead NFBGA Package

DESCRIPTION

The SCAN921025H transforms a 10-bit wide parallel

LVCMOS/LVTTL data bus into a single high speed

Bus LVDS serial data stream with embedded clock.

The SCAN921226H receives the Bus LVDS serial

data stream and transforms it back into a 10-bit wide

parallel data bus and recovers parallel clock.

Both devices are compliant with IEEE 1149.1

Standard for Boundary Scan Test. IEEE 1149.1

features provide the design or test engineer access

via a standard Test Access Port (TAP) to the

backplane or cable interconnects and the ability to

verify differential signal integrity. The pair of devices

also features an at-speed BIST mode which allows

the interconnects between the Serializer and

Deserializer to be verified at-speed.

The SCAN921025H transmits data over backplanes

or cable. The single differential pair data path makes

PCB design easier. In addition, the reduced cable,

PCB trace count, and connector size tremendously

reduce cost. Since one output transmits clock and

data bits serially, it eliminates clock-to-data and data-

to-data skew. The powerdown pin saves power by

reducing supply current when not using either device.

Upon power up of the Serializer, you can choose to

activate synchronization mode or allow the

Deserializer to use the synchronization-to-random-

data feature. By using the synchronization mode, the

Deserializer will establish lock to a signal within

specified lock times. In addition, the embedded clock

ensures a transition on the bus every 12-bit cycle.

This eliminates transmission errors due to charged

cable conditions. Furthermore, you may put the

SCAN921025H output pins into tri-state to achieve a

high impedance state. The PLL can lock to

frequencies between 20 MHz and 80 MHz.

•

APPLICATIONS

•

Automotive

Industrial

Military/Aerospace

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SCAN921025H, SCAN921226H

www.ti.com

SNLS185C – OCTOBER 2004 – REVISED MAY 2013

Functional Description

The SCAN921025H and SCAN921226H are a 10-bit Serializer and Deserializer chipset designed to transmit

data over differential backplanes at clock speeds from 20 to 80 MHz. The chipset is also capable of driving data

over Unshielded Twisted Pair (UTP) cable.

The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two

passive states: Powerdown and Tri-state. In addition to the active and passive states, there are also test modes

for JTAG access and at-speed BIST.

The following sections describe each operation and passive state and the test modes.

Initialization

Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of

the Serializer and Deserializer PLL's to local clocks, which may be the same or separate. Afterwards,

synchronization of the Deserializer to Serializer occurs.

Step 1: When you apply V

to both Serializer and/or Deserializer, the respective outputs enter tri-state, and on-

chip power-on circuitry disables internal circuitry. When V

reaches V

OK (2.5V) the PLL in each device

begins locking to a local clock. For the Serializer, the local clock is the transmit clock (TCLK) provided by the

source ASIC or other device. For the Deserializer, you must apply a local clock to the REFCLK pin.

The Serializer outputs remain in tri-state while the PLL locks to the TCLK. After locking to TCLK, the Serializer is

now ready to send data or SYNC patterns, depending on the levels of the SYNC1 and SYNC2 inputs or a data

stream. The SYNC pattern sent by the Serializer consists of six ones and six zeros switching at the input clock

rate.

Note that the Deserializer LOCK output will remain high while its PLL locks to the incoming data or to SYNC

patterns on the input.

Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will

lock to non-repetitive data patterns. However, the transmission of SYNC patterns enables the Deserializer to lock

to the Serializer signal within a specified time. See

Figure 17.

The user's application determines control of the SYNC1 and SYNC 2 pins. One recommendation is a direct

feedback loop from the LOCK pin. Under all circumstances, the Serializer stops sending SYNC patterns after

both SYNC inputs return low.

When the Deserializer detects edge transitions at the Bus LVDS input, it will attempt to lock to the embedded

clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK

is low, the Deserializer outputs represent incoming Bus LVDS data.

Data Transfer

After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to

latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data.

TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC

inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge.

After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the

embedded clock bits in the serial stream.

The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO±) at 12 times

the TCLK frequency. For example, if TCLK is 80 MHz, the serial rate is 80 × 12 = 960 Mega-bits-per-second.

Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if

TCLK = 80 MHz, the payload data rate is 80 × 10 = 800 Mbps. The data source provides TCLK and must be in

the range of 20 MHz to 80 MHz nominal.

The Serializer outputs (DO±) can drive a point-to-point connection or in limited multi-point or multi-drop

backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and

SYNC2 are low. When DEN is driven low, the Serializer output pins will enter tri-state.

Submit Documentation Feedback

Product Folder Links:

SCAN921025H SCAN921226H

SCAN921025H, SCAN921226H

SNLS185C – OCTOBER 2004 – REVISED MAY 2013

www.ti.com

When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the

embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise

ROUT0–ROUT9 is invalid.

The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled

by the RCLK_R/F input. See

Figure 14.

ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 80

MHz clock.

Resynchronization

When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the

Deserializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter tri-state.

The user's system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can

arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches

are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync

request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop

application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are

critical. However, the Deserializer can lock to random data, which is discussed in the next section.

Random Lock Initialization and Resynchronization

The initialization and resynchronization methods described in their respective sections are the fastest ways to

establish the link between the Serializer and Deserializer. However, the SCAN921226H can attain lock to a data

stream without requiring the Serializer to send special SYNC patterns. This allows the SCAN921226H to operate

in “open-loop” applications. Equally important is the Deserializer's ability to support hot insertion into a running

backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore,

because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time.

However, please see

Table 1

for some general random lock times under specific conditions. The primary

constraint on the “random” lock time is the initial phase relation between the incoming data and the REFCLK

when the Deserializer powers up. As described in the next paragraph, the data contained in the data stream can

also affect lock time.

If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as

the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than

one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN

9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the

Deserializer could become locked to the data pattern rather than the clock. Circuitry within the SCAN921226H

can detect that the possibility of “false lock” exists. The circuitry accomplishes this by detecting more than one

potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming

active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will

eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock

bits in the serial data stream. Graphical representations of RMT are shown in

Figure 2.

Please note that RMT

only applies to bits DIN0-DIN8.

Powerdown

When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the

Powerdown state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown

when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In

Powerdown, the PLL stops and the outputs enter tri-state, which disables load current and reduces supply

current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high.

Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the

devices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and

assert LOCK high until lock to the Bus LVDS clock occurs.

Submit Documentation Feedback

Product Folder Links:

SCAN921025H SCAN921226H

SCAN921025H, SCAN921226H

www.ti.com

SNLS185C – OCTOBER 2004 – REVISED MAY 2013

Tri-state

The Serializer enters tri-state when the DEN pin is driven low. This puts both driver output pins (DO+ and DO−)

into tri-state. When you drive DEN high, the Serializer returns to the previous state, as long as all other control

pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).

When you drive the REN pin low, the Deserializer enters tri-state. Consequently, the receiver output pins

(ROUT0–ROUT9) and RCLK will enter tri-state. The LOCK output remains active, reflecting the state of the PLL.

Table 1.

Random Lock Times for the SCAN921226H

(1)

80 MHz

Maximum

Mean

Minimum

Conditions:

(1)

Units

μs

3.0

0.43

PRBS 2 , V

= 3.3V

Difference in lock times are due to different starting points in the data pattern with multiple parts.

Test Modes

In addition to the IEEE 1149.1 test access to the digital TTL pins, the SCAN921025H and SCAN921226H have

two instructions to test the LVDS interconnects. The first is EXTEST. This is implemented at LVDS levels and is

only intended as a go no-go test (e.g. missing cables). The second method is the RUNBIST instruction. It is an

"at-system-speed" interconnect test. It is executed in approximately 28mS with a system clock speed of 80MHz.

There are two bits in the RX BIST data register for notification of PASS/FAIL and TEST_COMPLETE. Pass

indicates that the BER (Bit-Error-Rate) is better than 10

-7

An important detail is that once both devices have the RUNBIST instruction loaded into their respective

instruction registers, both devices must move into the RTI state within 4K system clocks (At a SCLK of 66Mhz

and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan

chain or LSP, however, it can be a problem with some multi-drop devices. This test mode has been simulated

and verified using TI's SCANSTA111.

DIN0 Held Low-DIN1 Held High Creates an RMT Pattern

DIN4 Held Low-DIN5 Held High Creates an RMT Pattern

Submit Documentation Feedback

Product Folder Links:

SCAN921025H SCAN921226H

Recommended Resources

IC801 internal circuit diagram

C534J1 vertical lathe control circuit 02

Toy police car circuit that can avoid obstacles

Buzzer replacement circuit for low light lamp

CAN interface circuit diagram

555 infrared alarm circuit

Fundamentals of Circuits and Analog Electronics Technology: This textbook mainly introduces the content of the basic course of circuit and analog electronic technology. The book has 10 chapters. Each chapter has a new section of "Design and Discussion Based on...; arui1999 Download Centre

Need a low current charging IC and a Bluetooth chip with integrated MCU: Need a low current charging IC and a Bluetooth chip with integrated MCUBattery specification: Lithium battery, platform voltage 3.7V, full charge 4.2V The required charging IC requirements are as foll...; QWE4562009 Test/Measurement

PCB Layout Guidelines: PCB Layout Guidelines[/b][/color][/size][/font][/align] [font=-apple-system-font, BlinkMacSystemFont, "][size=3][b][color=#0000ff] [/color][/b][/size][/font] [font=-apple-system-font, BlinkMacSystemFo...; btty038 PCB Design

LAUNCHXL-F28379D comprehensive routine: TI's official development board TMS320F28379D development board pre-installed comprehensive routines, understanding this routine is the best way to learn this TMS320F28379D chip Without further ado, t...; Aguilera DSP and ARM Processors

【DWIN Serial Port Screen】One of the Nucleic Acid Sampling and Registration Systems: [Preface] It has been almost three months since I came to EEWORLD. Here I can meet a lot of friends and learn a lot of knowledge. This time I applied for two screens from Devin to make a registration ...; lugl4313820 Domestic Chip Exchange

Live broadcast at 10 am today [TI's new generation MSP430 helps low-cost ultrasonic water meter]: Live Topic: Introduction and Quick Application Guide of TI's new generation MSP430 products in low-cost ultrasonic water metersLive broadcast time: 10:00-11:30 am, June 3, 2020 (Wednesday)Content Intr...; EEWORLD社区 Microcontroller MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components