GS8170DD36C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Features
• Double Data Rate Read and Write mode
• Late Write; Pipelined read operation
• JEDEC-standard SigmaRAM
™
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
18Mb
Σ
1x2Lp CMOS I/O
Double Data Rate SigmaRAM™
200 MHz–333 MHz
1.8 V V
DD
1.8 V I/O
Ne
w
GS8170DD36 SigmaRAMs are built in compliance with the
SigmaRAM pinout standard for synchronous SRAMs. They
are 18,874,368-bit (18Mb) SRAMs. This family of wide, very
low voltage CMOS I/O SRAMs is designed to operate at the
speeds needed to implement economical high performance
networking systems.
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
me
nd
ed
for
Σ
RAMs are offered in a number of configurations including
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Parameter Synopsis
Symbol
tKHKH
tKHQV
- 333
3.0 ns
1.8 ns
Key Fast Bin Specs
Cycle Time
Access Time
Rev: 2.03 1/2005
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De
sig
SigmaRAM Family Overview
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
n—
Di
sco
nt
inu
ed
Pr
od
u
Functional Description
cueing and data transfer rates. The
Σ
RAM
™
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing. In
DDR mode the device captures Data In on both rising and
falling edges of clock and drives data on both clock edges as
well.
Because the DDR
Σ
RAM always transfers data in two halves,
A0 is internally set to 0 for the first half of each read or write
transfer, and automatically incremented to 1 for the falling
edge transfer. The address field of a DDR
Σ
RAM is always
one address pin less than the advertised index depth (e.g., the
512k x 36 has a 512k addressable index).
Σ
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. DDR
Σ
RAMs incorporate rising-
and falling-edge-triggered output registers. They also utilize a
Dual Cycle Deselect (DCD) output deselect protocol.
Σ
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
ct
© 2002, GSI Technology, Inc.
GS8170DD36C-333/300/250/200
512K x 36 Common I/O—Top View (Package C)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
• 2002.06
•
NC
NC
NC
NC
NC
DQc
DQc
DQc
DQc
CQ2
NC
NC
NC
NC
DQd
DQd
DQd
DQd
DQd
NC
NC
NC
NC
DQc
DQc
DQc
DQc
DQc
CQ2
NC
NC
NC
NC
NC
DQd
DQd
DQd
A
MCL
NC
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CK
V
DDQ
V
SS
V
DDQ
V
SS
E2
NC
MCL
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
A
A
NC
(144M)
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
n—
Di
sco
nt
inu
ed
Pr
od
u
1
2
3
4
5
6
7
8
ct
9
10
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
DQa
NC
NC
NC
NC
11
DQb
DQb
DQb
DQb
DQb
NC
NC
NC
NC
CQ1
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
ADV
W
A
E3
A
A
MCL
NC
NC
NC
E1
NC
MCL
V
SS
MCL
V
DD
ZQ
NC
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
EP2
EP3
V
DD
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
De
sig
MCH
MCL
MCL
V
DD
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
Ne
w
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC
(36M)
A
A
MCH
MCH
MCL
V
DD
MCL
A
A1
MCL
me
nd
ed
for
V
SS
V
DDQ
V
SS
NC
A
V
DDQ
NC
A
A
TDI
TMS
V
DDQ
V
DD
V
SS
V
DD
NC
Re
co
m
NC
(72M)
A
A
DQd
11 x 19 Bump BGA—14 x 22 mm
2
Body—1 mm Bump Pitch
Note:
Users of CMOS I/O SigmaRAMs may wish to connect “NC, V
REF
” and the “NC, CK” pins to V
REF
(i.e., V
DDQ
/2) to allow alternate
use of future HSTL I/O SigmaRAMs.
Rev: 2.03 1/2005
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© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DD36C-333/300/250/200
Pin Description Table
Symbol
A
ADV
W
E1
E2 & E3
EP2 & EP3
CK
CQ, CQ
DQ
MCH
MCL
Description
Address
Advance
Write Enable
Chip Enable
Chip Enable
Chip Enable Program Pin
Clock
Echo Clock
Data I/O
Must Connect High
Must Connect Low
Type
Input
Input
Input
Input
Input
Comments
—
Active Low
Active High
Active Low
Mode Input
Input
Output
Input/Output
Input
Input
ZQ
TCK
TDI
TDO
TMS
NC
V
DD
V
DDQ
V
SS
Output Impedance Control
Test Clock
Test Data In
Test Data Out
Test Mode Select
No Connect
De
sig
Mode Input
Input
Ne
w
Input
Output
Input
—
Input
Input
Input
me
nd
ed
for
Core Power Supply
Output Driver Power Supply
Ground
Operation Control
Rev: 2.03 1/2005
No
t
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Re
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m
3/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
n—
Di
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Pr
od
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—
—
—
—
Programmable Active High or Low
To be tied directly to V
DD
, V
DDQ
or V
SS
Active High
Three State - Deselect via E2 or E3 False
Three State
Active High
To be tied directly to V
DD
or V
DDQ
Active Low
To be tied directly to V
SS
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
To be tied directly to V
DDQ
or V
SS
Active High
Not connected to die or any other pin
1.8 V Nominal
1.8 V Nominal
ct
© 2002, GSI Technology, Inc.
GS8170DD36C-333/300/250/200
Read Operations
Double Data Rate Read
In applications where a data rate markedly faster than the RAM’s latency is desired, the Double Data Rate protocol doubles the
data transfer rate (read or write bandwidth) achieved in Pipeline mode while keeping the RAM’s clock frequency constant. In
Double Data Rate mode, the RAM multiplexes the results of a read out of the RAM on half the usual number of data pins. The
output register/mux behaves just as if it were in Pipeline mode for the first transfer, but then makes a second transfer in response to
the next falling edge of clock as well. SigmaRAM DDR RAMs burst in linear order only.
Double Data Rate Pipelined Read
Read
CK
Deselect
Read
Read
Address
A
XX
C
n—
Di
sco
nt
inu
ed
Pr
od
u
Read
D
E
QC0
QC1
Access
ct
F
ADV
/E
1
QA0
DQ
QA1
De
sig
/W
QD0
QD1
CQ
Ne
w
me
nd
ed
for
Hi-Z
Key
Write Operations
Double Data Rate Write
A Double Data Rate Write is a specialized form of Late Write. In Double Data Rate mode, the RAM will capture Data In on both
rising and falling edges of the RAM clock, CK, beginning with the rising edge of clock that follows the capture of the write address
and command.
Rev: 2.03 1/2005
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Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
4/29
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8170DD36C-333/300/250/200
SigmaRAM Double Data Rate Read and Write
Read
CK
Deselect
Write
Read
Read
Address
A
B
C
n—
Di
sco
nt
inu
ed
Pr
od
u
D
E
DC0
DC1
Key
Access
ct
F
ADV
/E
1
/W
QA0
DQ
QA1
QD0
QD1
CQ
Hi-Z
Rev: 2.03 1/2005
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nd
ed
for
5/29
Ne
w
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sig
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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