MO2002
High Frequency, Single Chip, One-output Clock Generator
Features
Applications
Any frequency between 115 MHz to 137 MHz accurate to 6 decimal
places of accuracy
Operating temperature from -40°C to +85°C. Refer to MO2019 for
-40°C to +125°C and MO2021 for -55°C to +125°C options
Excellent total frequency stability as low as ±20 PPM
Low power consumption of +4.9 mA typical at 125 MHz, +1.8V
LVCMOS/LVTTL compatible output
5-pin SOT23-5: 2.9mm x 2.8mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to MO2024 and MO2025
GEPON, network switches, routers, servers, embedded
systems, industrial and medical devices
Ethernet, PCI-E, DDR, etc.
Electrical Specifications
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are
at +25°C and nominal supply voltage.
Parameters
Output Frequency Range
Symbol
f
Min.
115
-20
Frequency Stability
F_stab
-25
-50
-20
-40
+1.62
+2.25
Supply Voltage
Vdd
+2.52
+2.7
+2.97
+2.25
–
Current Consumption
Idd
–
–
OE Disable Current
I_od
–
–
–
Standby Current
I_std
–
–
Duty Cycle
Rise/Fall Time
DC
Tr, Tf
45
–
–
–
Output High Voltage
VOH
90%
Typ.
–
–
–
–
–
–
+1.8
+2.5
+2.8
+3.0
+3.3
–
+6.2
+5.5
+4.9
–
–
+2.6
+1.4
+0.6
–
1.0
1.3
1.0
–
Max.
137
+20
+25
+50
+70
+85
+1.98
+2.75
+3.08
+3.3
+3.63
+3.63
+7.5
+6.4
+5.6
+4.3
+4.1
+4.3
+2.5
+1.3
55
2.0
2.5
2.0
–
Unit
MHz
PPM
PPM
PPM
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
mA
μA
μA
μA
%
ns
ns
ns
Vdd
No load condition, f = 125 MHz,
Vdd = +2.8V, +3.0V, +3.3V or +2.25 to +3.63V
No load condition, f = 125 MHz, Vdd = +2.5V
No load condition, f = 125 MHz, Vdd = +1.8V
Vdd = +2.5V to +3.3V, OE = Low, Output in high Z state
Vdd = +1.8V, OE = Low, Output in high Z state
Vdd = +2.8V to +3.3V,
ST
= Low, Output is weakly pulled down
Vdd = +2.5V,
ST
= Low, Output is weakly pulled down
Vdd = +1.8V,
ST
= Low, Output is weakly pulled down
All Vdds
Vdd = +2.5V, +2.8V, +3.0V or +3.3V, 20% - 80%
Vdd =+1.8V, 20% - 80%
Vdd = +2.25V - +3.63V, 20% - 80%
IOH = -4.0 mA (Vdd = +3.0V or +3.3V)
IOH = -3.0 mA (Vdd = +2.8V and Vdd = +2.5V)
IOH = -2.0 mA (Vdd = +1.8V)
IOL = +4.0 mA (Vdd = +3.0V or +3.3V)
IOL = +3.0 mA (Vdd = +2.8V and Vdd = +2.5V)
IOL = +2.0 mA (Vdd = +1.8V)
Condition
Frequency Range
Frequency Stability and Aging
Inclusive of Initial tolerance at +25°C, 1st year aging at +25°C,
and variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Operating Temperature Range
Operating Temperature Range
(Ambient)
T_use
Extended Commercial
Industrial
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Output Low Voltage
VOL
–
–
10%
Vdd
Input Characteristics
Input High Voltage
Input Low Voltage
Input Pull-up Impedance
VIH
VIL
Z_in
70%
–
50
2.0
–
–
87
–
–
30%
150
–
Vdd
Vdd
kΩ
MΩ
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
+81-79-426-3211
www.kds.info
Revised September 29, 2015
Daishinku Corp.
Rev. 1.01
1389 Shinzaike, Hiraoka-cho, Kakogawa, Hyogo 675-0194 Japan
MO2002
High Frequency, Single Chip, One-output Clock Generator
Table 1. Electrical Characteristics (continued)
Parameters
Symbol
Min.
–
–
–
–
–
–
–
–
–
Typ.
–
–
–
1.9
1.6
12
14
0.5
1.3
Max.
Unit
Condition
Startup and Resume Timing
Startup Time
Enable/Disable Time
Resume Time
T_start
T_oe
T_resume
5.0
130
5.0
Jitter
3.0
4.0
20
30
0.9
2.0
ps
ps
ps
ps
ps
ps
RMS Period Jitter
T_jitt
f = 125 MHz, Vdd = +2.5V, +2.8V, +3.0V or +3.3V
f = 125 MHz, Vdd = +1.8V
f = 125 MHz, Vdd = +2.5V, +2.8V, +3.0V or +3.3V
f = 125 MHz, Vdd = +1.8V
Integration bandwidth = 900 kHz to 7.5 MHz
Integration bandwidth = 12 kHz to 20 MHz
ms
ns
ms
Measured from the time Vdd reaches its rated minimum value
f = 115 MHz. For other frequencies, T_oe = 100 ns + 3 * clock
periods
Measured from the time
ST
pin crosses 50% threshold
Peak-to-peak Period Jitter
T_pk
RMS Phase Jitter (random)
T_phj
Table 2. Pin Description
Pin
1
2
Symbol
GND
NC
Power
No Connect
Output
Enable
3
OE/ ST/NC
Standby
Electrical ground
No connect
H
[1]
: specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[1]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Any voltage between 0 and Vdd or Open
[1]
: Specified frequency
output. Pin 3 has no function.
Power supply voltage
[2]
Oscillator output
4
Top View
Functionality
OE/ST/NC NC
3
2
GND
1
No Connect
4
5
Notes:
VDD
OUT
Power
Output
5
VDD
OUT
Figure 1. Pin Assignments
1. In OE or
ST
mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven. If
pin 3 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev. 1.01
Page 2 of 11
www.kds.info
MO2002
High Frequency, Single Chip, One-output Clock Generator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
Vdd
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
[3]
Min.
-65
-0.5
–
–
–
Max.
+150
+4.0
+2000
+260
+150
Unit
°C
V
V
°C
°C
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration
[4]
Package
SOT23-5
JA
, 4 Layer Board
(°C/W)
421
JC
, Bottom
(°C/W)
175
Note:
4. Refer to JESD51 for
JA
and
JC
definitions, and reference layout used to determine the
JA
and
JC
values in the above table.
Table 5. Maximum Operating Junction Temperature
[5]
Max Operating Temperature
+70°C
+85°C
Maximum Operating Junction Temperature
+80°C
+95°C
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.01
Page 3 of 11
www.kds.info
MO2002
High Frequency, Single Chip, One-output Clock Generator
Test Circuit and Waveform
[6]
Test
Point
Vout
Vdd
Tr
5
4
0.1µF
Power
Supply
Tf
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
15 pF
(including probe
and fixture
capacitance)
1
2
3
Ω
1k
Vdd
OE/ST Function
Figure 2. Test Circuit
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Figure 3. Output Waveform
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
Pin 4 Voltage
T_start
No Glitch
during start up
[7]
ST Voltage
T_resume
CLK Output
HZ
CLK Output
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
Vdd
50% Vdd
T_oe
OE Voltage
Figure 5. Standby Resume Timing (ST Mode Only)
Vdd
OE Voltage
50% Vdd
T_oe
CLK Output
HZ
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Note:
7. MO2002 has “no runt” pulses and “no glitch” output during startup or resume.
Figure 7. OE Disable Timing (OE Mode Only)
Rev. 1.01
Page 4 of 11
www.kds.info
MO2002
High Frequency, Single Chip, One-output Clock Generator
Performance Plots
[8]
1.8
7.5
20
7.0
15
2.5
2.8
3.0
3.3
DUT1
DUT6
DUT2
DUT7
DUT3
DUT8
DUT4
DUT9
DUT5
DUT10
Frequency (ppm)
6.5
6.0
5.5
5.0
4.5
4.0
115
117
119
121
123
125
127
129
131
133
135
137
10
5
0
-5
-10
-15
-20
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Idd (mA)
Frequency (MHz)
Temperature (°C)
Figure 8. Idd vs Frequency
Figure 9. Frequency vs Temperature, +1.8V
1.8 V
4.0
3.5
2.5 V
2.8 V
3.0 V
3.3 V
55
54
53
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
RMS period jitter (ps)
3.0
2.5
2.0
1.5
1.0
47
0.5
0.0
115
117
119
121
123
125
127
129
131
133
135
137
46
45
115
117
119
121
123
125
127
129
131
133
135
137
Duty cycle (%)
Frequency (MHz)
52
51
50
49
48
Frequency (MHz)
Figure 10. RMS Period Jitter vs Frequency
Figure 11. Duty Cycle vs Frequency
1.8 V
2.5
2.5 V
2.8 V
3.0 V
3.3 V
2.5
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
2.0
2.0
Rise time (ns)
1.5
Fall time (ns)
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
1.5
1.0
1.0
0.5
0.5
0.0
0.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (°C)
Temperature (°C)
Figure 12. 20%-80% Rise Time vs Temperature
Figure 13. 20%-80% Fall Time vs Temperature
Rev. 1.01
Page 5 of 11
www.kds.info
京公网安备 11010802033920号
EEWORLD
