EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

SL8BLF-02-2580-DC

Description
Array/Network Resistor, Bussed, 0.8W, 100V, 0.5% +/-Tol, 50ppm/Cel, Surface Mount, 3040, SOIC, LEAD FREE
CategoryPassive components    The resistor   
File Size277KB,4 Pages
ManufacturerTT Electronics plc
Websitehttp://www.ttelectronics.com/
Environmental Compliance  
Download Datasheet Parametric View All

SL8BLF-02-2580-DC Overview

Array/Network Resistor, Bussed, 0.8W, 100V, 0.5% +/-Tol, 50ppm/Cel, Surface Mount, 3040, SOIC, LEAD FREE

SL8BLF-02-2580-DC Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid2008841568
package instruction, 3040
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresPRECISION
Component power consumption0.05 W
The first element resistor258 Ω
JESD-609 codee3
Manufacturer's serial numberSOIC
Installation featuresSURFACE MOUNT
Network TypeBUSSED
Number of components15
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingTR; TUBE
Rated power dissipation(P)0.8 W
Rated temperature70 °C
Resistor typeARRAY/NETWORK RESISTOR
size code3040
surface mountYES
Temperature Coefficient50 ppm/°C
Temperature coefficient tracking20 ppm/°C
Terminal surfaceMatte Tin (Sn)
Terminal shapeGULL WING
Tolerance0.5%
Operating Voltage100 V
FAQ_How to test Mesh low power nodes
Author: Lucien KUANG, ST engineerClick to download the pdf document to view:Keywords: BlueNRG-1, BlueNRG-2, Mesh, low power consumptionQuestion: After getting our boards, many friends want to know whe...
nmg ST - Low Power RF
STM32F207
Our company has authentic original factory order (Mouser) stm32f207vet6 1000pcs price preferential, WeChat 1875387499...
chlegay stm32/stm8
How to Suppress Zero Drift in Direct-Coupled Amplifier Circuits
0 Introduction Direct coupling is the simplest way to connect stages. It is to directly connect the input of the latter stage with the output of the previous stage. The coupling method in which the ou...
led2015 Power technology
FPGA Implementation of Digital Signal Processing.pdf
FPGA Implementation of Digital Signal Processing.pdf...
zxopenljx EE_FPGA Learning Park
Phase-Locked Loop (PLL) Basics
Phase-Locked Loop (PLL) Basics A phase-locked loop is a feedback system in which a voltage-controlled oscillator (VCO) and a phase comparator are connected so that the oscillator can maintain a consta...
qwqwqw2088 Analogue and Mixed Signal
【GD32450I-EVAL】+ 03 Basic usage of library functions - taking key interrupt as an example
[i=s]This post was last edited by DDZZ669 on 2020-9-18 22:05[/i]The previous article " 【GD32450I-EVAL】+ 02 Software Development Environment Configuration (KEIL 5) and Running Light Test " introduced t...
DDZZ669 GD32 MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号