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RPC564L60L5BFSR

Description
microcontroller for Aerospace and Defense, SIL3/ASILD safety applications
File Size1MB,137 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
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RPC564L60L5BFSR Overview

microcontroller for Aerospace and Defense, SIL3/ASILD safety applications

RPC56EL60L5
32-bit Power Architecture
®
microcontroller
for Aerospace and Defense, SIL3/ASILD safety applications
Datasheet
-
production data
LQFP144 (20 x 20 x 1.4 mm)
– Power management unit (PMU)
– Cyclic redundancy check (CRC) unit
Decoupled Parallel mode for high-performance
use of replicated cores
Nexus Class 3+ interface
GPIOs individually programmable as input,
output or special function
Three 6-channel general-purpose eTimer units
2 FlexPWM units: 4 16-bit channels per module
Communications interfaces
– 2 LINFlexD channels
– 3 DSPI channels
– 2 FlexCAN interfaces (2.0B Active)
– FlexRay module (V2.1 Rev. A)
Two 12-bit analog-to-digital converters (ADCs)
– 16 input channels
– Programmable CTU to synchronize ADCs
conversion with timer and PWM
Sine wave generator (D/A with low pass filter)
Single 3.0 V to 3.6 V voltage supply
Ambient temperature range –40 °C to 125 °C
Junction temperature range –40 °C to 150 °C
Aerospace and Defense features
– Dedicated traceability and part marking
– Production parts approval documents
available
– Adapted Extended life time and
obsolescence management
– Extended Product Change Notification
process
– Designed and manufactured to meet sub
ppm quality goals
– Advanced mold and frame designs for
Superior resilience to harsh environment
(acceleration, EMI, thermal, humidity)
– Single Fabrication, Assembly and Test site
– Dual internal production source capability
Features
High-performance e200z4d dual core
32-bit Power Architecture® technology CPU
Core frequency as high as 120 MHz
Dual issue five-stage pipeline core
Variable Length Encoding (VLE)
Memory Management Unit (MMU)
4 KB instruction cache with error detection
code
Signal processing engine (SPE)
Memory available
– 1 MB flash memory with ECC
– 128 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM
emulation
SIL3/ASILD innovative safety concept:
LockStep mode and Fail-safe protection
– Sphere of replication (SoR) for key
components (such as CPU core, eDMA,
crossbar switch)
– FCCU, interrupt controller
– Redundancy control and checker unit
(RCCU) on outputs of the SoR connected
to FCCU
– Boot-time Built-In Self-Test for Memory
(MBIST) and Logic (LBIST) triggered by
hardware
– Boot-time Built-In Self-Test for ADC and
flash memory triggered by software
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
September 2014
This is information on a product in full production.
DocID026934 Rev 1
1/137
www.st.com

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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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