MT46H16M32LFBQ-5AAT:C datasheet, PDF

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MT46H16M32LFBQ-5AAT:C: DescriptionDDR DRAM, 16MX32, 5ns, CMOS, PBGA90, 8 X 13 MM, GREEN, PLASTIC, VFBGA-90; Categorystorage storage; File Size1MB，96 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT46H16M32LFBQ-5AAT:C Overview

DDR DRAM, 16MX32, 5ns, CMOS, PBGA90, 8 X 13 MM, GREEN, PLASTIC, VFBGA-90

MT46H16M32LFBQ-5AAT:C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	1100345964
Parts packaging code	BGA
package instruction	VFBGA, BGA90,9X15,32
Contacts	90
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
interleaved burst length	2,4,8,16
JESD-30 code	R-PBGA-B90
JESD-609 code	e1
length	13 mm
memory density	536870912 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	90
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	16MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA90,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	1.8 V
Certification status	Not Qualified
refresh cycle	8192
Filter level	AEC-Q100
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	2,4,8,16
Maximum standby current	0.000015 A
Maximum slew rate	0.115 mA
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

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512Mb: x16, x32 Automotive LPDDR SDRAM

Features

Automotive LPDDR SDRAM

MT46H32M16LF – 8 Meg x 16 x 4 banks

MT46H16M32LF – 4 Meg x 32 x 4 banks

MT46H16M32LG – 4 Meg x 32 x 4 banks

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh, 32ms for automotive temperature

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-6

Clock Rate

200 MHz

166 MHz

Access Time

5.0ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

– 16 Meg x 32 (4 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard addressing

• Plastic "green" package

– 60-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• Timing – cycle time

– 5ns @ CL = 3 (200 MHz)

– 6ns @ CL = 3 (166 MHz)

• Power

– Standard I

DD2

DD6

– Low-power I

DD2

DD6

• Product certification

– Automotive

• Operating temperature range

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Design revision

Notes:

Marking

32M16

16M32

-5

-6

None

1. Only available for x16 configuration.

2. Only available for x32 configuration.

PDF: 09005aef846e285e

t67m_embedded_lpddr_512mb.pdf - Rev. D 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb: x16, x32 Automotive LPDDR SDRAM

Features

Contents

General Description ......................................................................................................................................... 8

Functional Block Diagrams ............................................................................................................................... 9

Ball Assignments ............................................................................................................................................ 11

Ball Descriptions ............................................................................................................................................ 13

Package Dimensions ....................................................................................................................................... 15

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – I

Parameters ........................................................................................................ 21

Electrical Specifications – AC Operating Conditions ......................................................................................... 27

Output Drive Characteristics ........................................................................................................................... 31

Functional Description ................................................................................................................................... 34

Commands .................................................................................................................................................... 35

DESELECT ................................................................................................................................................. 36

NO OPERATION ......................................................................................................................................... 36

LOAD MODE REGISTER ............................................................................................................................. 36

ACTIVE ...................................................................................................................................................... 36

READ ......................................................................................................................................................... 37

WRITE ....................................................................................................................................................... 38

PRECHARGE .............................................................................................................................................. 39

BURST TERMINATE ................................................................................................................................... 40

AUTO REFRESH ......................................................................................................................................... 40

SELF REFRESH ........................................................................................................................................... 41

DEEP POWER-DOWN ................................................................................................................................. 41

Truth Tables ................................................................................................................................................... 42

State Diagram ................................................................................................................................................ 47

Initialization .................................................................................................................................................. 48

Standard Mode Register .................................................................................................................................. 51

Burst Length .............................................................................................................................................. 52

Burst Type .................................................................................................................................................. 52

CAS Latency ............................................................................................................................................... 53

Operating Mode ......................................................................................................................................... 54

Extended Mode Register ................................................................................................................................. 55

Temperature-Compensated Self Refresh ...................................................................................................... 55

Partial-Array Self Refresh ............................................................................................................................ 56

Output Drive Strength ................................................................................................................................ 56

Status Read Register ....................................................................................................................................... 57

Bank/Row Activation ...................................................................................................................................... 59

READ Operation ............................................................................................................................................. 60

WRITE Operation ........................................................................................................................................... 71

PRECHARGE Operation .................................................................................................................................. 83

Auto Precharge ............................................................................................................................................... 83

Concurrent Auto Precharge ......................................................................................................................... 84

AUTO REFRESH Operation ............................................................................................................................. 89

SELF REFRESH Operation ............................................................................................................................... 90

Power-Down .................................................................................................................................................. 91

Deep Power-Down ..................................................................................................................................... 93

Clock Change Frequency ................................................................................................................................ 95

Revision History ............................................................................................................................................. 96

Rev. D – 02/14 ............................................................................................................................................. 96

Rev. C – 11/13 ............................................................................................................................................. 96

Rev. B – 03/13 ............................................................................................................................................. 96

PDF: 09005aef846e285e

t67m_embedded_lpddr_512mb.pdf - Rev. D 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x16, x32 Automotive LPDDR SDRAM

Features

List of Figures

Figure 1: 512Mb Mobile LPDDR Part Numbering .............................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12

Figure 6: 60-Ball VFBGA (8mm x 9mm); Package Code: BF .............................................................................. 15

Figure 7: 90-Ball VFBGA (8mm x 13mm); Package Codes: B5 (SAC105), BQ (SAC305) ........................................ 16

Figure 8: SSTL Clock Input ............................................................................................................................. 19

Figure 9: Differential Clock Amplitude ........................................................................................................... 19

Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 26

Figure 11: ACTIVE Command ........................................................................................................................ 37

Figure 12: READ Command ........................................................................................................................... 38

Figure 13: WRITE Command ......................................................................................................................... 39

Figure 14: PRECHARGE Command ................................................................................................................ 40

Figure 15: DEEP POWER-DOWN Command ................................................................................................... 41

Figure 16: Simplified State Diagram ............................................................................................................... 47

Figure 17: Initialize and Load Mode Registers ................................................................................................. 49

Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 50

Figure 19: Standard Mode Register Definition ................................................................................................. 51

Figure 20: CAS Latency .................................................................................................................................. 54

Figure 21: Extended Mode Register ................................................................................................................ 55

Figure 22: Status Read Register Timing ........................................................................................................... 57

Figure 23: Status Register Definition .............................................................................................................. 58

Figure 24: READ Burst ................................................................................................................................... 61

Figure 25: Consecutive READ Bursts .............................................................................................................. 62

Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 63

Figure 27: Random Read Accesses .................................................................................................................. 64

Figure 28: Terminating a READ Burst ............................................................................................................. 65

Figure 29: READ-to-WRITE ............................................................................................................................ 66

Figure 30: READ-to-PRECHARGE .................................................................................................................. 67

Figure 31: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 68

Figure 32: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 69

Figure 33: Data Output Timing –

AC and

DQSCK .......................................................................................... 70

Figure 34: Data Input Timing ......................................................................................................................... 72

Figure 35: Write – DM Operation .................................................................................................................... 73

Figure 36: WRITE Burst ................................................................................................................................. 74

Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 75

Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 75

Figure 39: Random WRITE Cycles .................................................................................................................. 76

Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 77

Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 78

Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 79

Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 80

Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 81

Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 82

Figure 46: Bank Read – With Auto Precharge ................................................................................................... 85

Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 86

Figure 48: Bank Write – With Auto Precharge .................................................................................................. 87

Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 88

Figure 50: Auto Refresh Mode ........................................................................................................................ 89

PDF: 09005aef846e285e

t67m_embedded_lpddr_512mb.pdf - Rev. D 2/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT46H16M32LFBQ-5AAT:C Related Products

	MT46H16M32LFBQ-5AAT:C	MT46H32M16LFBF-5IT:CTR	MT46H32M16LFBF-6IT:CTR
Description	DDR DRAM, 16MX32, 5ns, CMOS, PBGA90, 8 X 13 MM, GREEN, PLASTIC, VFBGA-90	DDR DRAM, 32MX16, 5ns, CMOS, PBGA60, 8 X 9 MM, GREEN, PLASTIC, VFBGA-60	DDR DRAM, 32MX16, 5ns, CMOS, PBGA60, 8 X 9 MM, GREEN, PLASTIC, VFBGA-60
Is it Rohs certified?	conform to	conform to	conform to
package instruction	VFBGA, BGA90,9X15,32	VFBGA,	VFBGA,
Reach Compliance Code	compliant	compliant	unknown
ECCN code	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5 ns	5 ns	5 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B90	R-PBGA-B60	R-PBGA-B60
JESD-609 code	e1	e1	e1
length	13 mm	9 mm	9 mm
memory density	536870912 bit	536870912 bit	536870912 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM
memory width	32	16	16
Number of functions	1	1	1
Number of ports	1	1	1
Number of terminals	90	60	60
word count	16777216 words	33554432 words	33554432 words
character code	16000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	105 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C
organize	16MX32	32MX16	32MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VFBGA	VFBGA	VFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260
Maximum seat height	1 mm	1 mm	1 mm
self refresh	YES	YES	YES
Maximum supply voltage (Vsup)	1.95 V	1.95 V	1.95 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	30	30
width	8 mm	8 mm	8 mm
Maker	-	Micron Technology	Micron Technology

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