PHR0603C2840BGW datasheet, PDF

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PHR0603C2840BGW: DescriptionRes,SMT,Thin Film,284 Ohms,35WV,.1% +/-Tol,-5,5ppm TC,0603 Case; CategoryPassive components The resistor; File Size113KB，6 Pages; ManufacturerVishay; Websitehttp://www.vishay.com

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PHR0603C2840BGW Overview

Res,SMT,Thin Film,284 Ohms,35WV,.1% +/-Tol,-5,5ppm TC,0603 Case

PHR0603C2840BGW Parametric

Parameter Name	Attribute value
Objectid	256145845
package instruction	SMT, 0603
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	HIGH PRECISION
structure	Rectangular
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	2
Maximum operating temperature	155 °C
Minimum operating temperature	-65 °C
Package height	1.02 mm
Package length	2.16 mm
Package form	SMT
Package width	1.01 mm
method of packing	Waffle Pack
Rated power dissipation(P)	0.1 W
Rated temperature	70 °C
Guideline	ESCC4001/023
resistance	284 Ω
Resistor type	FIXED RESISTOR
size code	0603
surface mount	YES
technology	THIN FILM
Temperature Coefficient	5 ppm/°C
Terminal surface	Gold (Au)
Terminal shape	WRAPAROUND
Tolerance	0.1%
Operating Voltage	35 V

PHR0603C2840BGW Preview

PHR

www.vishay.com

Vishay Sfernice

ESCC (

) 4001/023 Qualified High Precision (5 ppm, 0.01 %),

Thin Film Chip Resistors

FEATURES

• Load life stability at ± 70 °C for 2000 h:



0.15 % under Pn

• Low temperature coefficient down to ± 5 ppm/°C

• Very low noise (< -35 dB) and voltage coefficient

(< 0.01 ppm/V)

DESIGN SUPPORT TOOLS

Models

Available

click logo to get started

• Resistance range: 10



to 3 M (depending on size)

• Laser trimmed tolerances to ± 0.01 %

• TCR in lot tracking



5 ppm/°C

• Termination: Thin film technology

• SnPb terminations over nickel barrier

• ESCC 4001 (generic specifications)

• ESCC 4001/023 (detailed specifications)

• ESCC qualified

• SMD wraparound chip resistor

• Operating temperature range: -65 °C to +155 °C

• From 0402 to 2010

• Material categorization: for definitions of compliance

please see

www.vishay.com/doc?99912

Vishay Sfernice Thin Film division holds ESCC QML

qualification (ESCC technology flow qualification).

These High-Rel. components are ideal for low noise and

precision applications, superior stability, low temperature

coefficient of resistance, and low voltage coefficient, Vishay

Sfernice’s precision thin film wraparound resistors exceed

requirements of MIL-PRF-55342G characteristics Y

(± 10 ppm/°C).

STANDARD ELECTRICAL SPECIFICATIONS

MODEL

ESCC

SIZE VARIANT

NUMBER

0402 13 and 14

0603 01 and 05

0805 02 and 06

1206 03 and 07

2010 04 and 08

RATED

POWER

RESISTANCE

AT + 70 °C

RANGE

(Pn)



(1)

10 to 150K

10 to 500K

10 to 750K

10 to 3.5M

10 to 6M

0.05

0.1

0.125

0.25

0.50

LIMITING

ELEMENT

VOLTAGE

(UL)

(1)

100

150

INSULATION

VOLTAGE

)

100

200

300

TOLERANCE

±%

0.01, 0.02, 0.05, 0.1

TEMPERATURE

COEFFICIENT

± ppm/°C

5, 10, 25

PHR 0402

PHR 0603

PHR 0805

PHR 1206

PHR 2010

Note

(1)

Limiting voltages and power rating are already derated (for maximum ratings admissible, refer to P chip:

www.vishay.com/cod?53017)

CLIMATIC SPECIFICATIONS

Operating temperature

range

Soldering temperature

sol

)

-65 °C; +155 °C

260 °C, immersion 10 s

MECHANICAL SPECIFICATIONS

Substrate material

Technology

Film

Protection

Terminations

Alumina

Thin film

Nickel chromium

with mineral



passivation

Epoxy and silicone

B type:

SnPb over nickel barrier

for solder reflow

(1)



G type:

gold over nickel barrier

Note

(1)

For B terminations use recommended reflow profile #1 as per

Application Note “Guidelines for Vishay Sfernice Resistive and

Inductive Components” (document number: 52029)

Revision: 03-Jan-2019

Document Number: 53037

For technical questions, contact:

sferthinfilm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

PHR

www.vishay.com

Vishay Sfernice

DIMENSIONS

in millimeters

VARIANT

NUMBER

01, 05

02, 06

03, 07

04, 08

13, 14

STYLE

0603

0805

1206

2010

0402

MIN.

1.39

1.78

2.87

4.95

0.87

MAX.

2.16

2.55

3.64

5.72

1.64

MIN.

0.62

1.14

1.47

2.41

0.47

MAX.

1.01

1.53

1.86

2.8

0.86

DIMENSIONS

MIN.

MAX.

0.25

1.02

0.25

1.02

0.25

1.02

0.25

1.02

0.25

1.02

MIN.

0.17

0.35

0.09

MAX.

0.51

0.85

0.38

MIN.

0.25

0.35

0.12

MAX.

0.51

0.85

0.38

TRACEABILITY DEFINITIONS

The two major traceability elements are defined as:

• The primary process lot number named Front End lot (FE lot). One “FE lot” is composed of several wafers issued from the

same thin film deposition sequence.

• The date code named Batch Number (BN). The “BN” is defined after completion of the end of production testing sequence.

The lot homogeneity is given by the “FE lot” and not by the “BN”.

According to the applied rules validated by the ESCC through the product qualification, the following situations are agreed:

• Parts coming from different “FE lost” might have the same “BN”.

• A maximum of two different “BN” might be applied to the same “FE lot” to enable the use of overruns from a previous PO.

• Unless requested / approved by the customer the “BN” will be 2 years old maximum.

SPECIFIC TRACEABILITY REQUIREMENTS

The following specific requirements have to be treated as:

• A customer who requires “Lot Homogeneity” has to mention it on the PO as “SINGLE PRODUCTION LOT”.

• A customer who requires “Lot Homogeneity” in addition to a “Single Batch Number” has to mention it on the PO as “SINGLE

PRODUCTION LOT AND OPTION R0101”.

END OF PRODUCTION TESTING

Mandatory testing performed at the end of the production process:

• 100 % overload: Voltage



6.25 Pn x Rn



or 2 UL whichever is less - duration 2 s

• 100 % burn in: 168 h at Pn at 70 °C

OPTIONS

LOT VALIDATION TESTING

For procurement of qualified components, lot validation testing is not required and shall only be performed if specifically

stipulated in the purchase order.

For procurement of unqualified components, lot validation testing shall be performed as stipulated in the purchase order. The

need for lot validation testing shall be determined by the orderer.

When lot validation testing is required, it shall consist of the performance of one or more of the tests or subgroup test sequences

of chart F4 indicated in the ESA Generic Specification ESCC 4001. The testing to be performed and the sample size shall be as

stipulated in the purchase order. When procurement of more than one component type is involved from a family, range or series,

the selection of representative samples shall also be stipulated in the purchase order.

Lot validation testing will be composed of one LVT charges and LVT samples:

• Lot validation test charges has to be ordered separately on purchase order.

• Lot validation samples have to be ordered separately on purchase orderer.

FINAL INSPECTION

If requested by the orderer a final inspection can be performed on site.

Final inspection has to be stipulated separately on purchase order.

Revision: 03-Jan-2019

Document Number: 53037

For technical questions, contact:

sferthinfilm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

PHR

www.vishay.com

Vishay Sfernice

LAND PATTERN

in millimeters

min.

max.

CHIP SIZE

0402

0603

0805

1206

2010

max.

1.55

2.37

2.76

3.91

5.93

min.

0.15

0.35

0.74

1.85

3.71

max.

0.73

0.98

1.40

1.73

2.67

Note

• Suggested land pattern: According to IPC-7351A

QUALIFIED OHMIC RANGE

MODEL

ESCC

VARIANT

OHMIC

RANGE

()

10 to < 50

01 to 08

and

13 to 14

50 to < 100

100 to < 250



250

(1)

QUALIFIED OHMIC RANGE

TOLERANCE

(%)

0.1

0.05 and 0.1

PHR

0.02, 0.05 and 0.1

01 to 08

and

13 to 14

MODEL

ESCC

VARIANT

OHMIC

RANGE

()

(1)

TEMPERATURE

COEFFICIENT

(ppm/°C)

ESCC

CODE

10 to < 20 E: 25 (-55 °C; +155 °C)

E : 25 (-55 °C ; +155 °C)

20 to < 50 Y : 10 (-55 °C ; +155 °C)

Z : 5 (+22 °C ; +70 °C)



E : 25 (-55 °C ; +155 °C)

Y : 10 (-55 °C ; +155 °C)

Z : 5 (+22 °C ; +70 °C)

C : 5 (-55 °C ; +155 °C)

PHR

0.01, 0.02, 0.05 and 0.1

(1)

QUALIFIED OHMIC RANGE: MAX. VALUE

PHR 0402

PHR 0603

100 k (67 k for TCR C) 200 k (160 k for TCR C)

PHR 0805

250 k

PHR 1206

1 M

PHR 2010

3 M

Note

(1)

For values, TCR, tolerance outside of qualified range: Please consult

POPULAR OPTIONS

OPTION 0041

Production according to ESCC 4001/023 for: Cases, ohmic

values, tolerance or TCR outside of qualified range.

Please consult Vishay Sfernice for feasibility.

EXTENDED FEATURES

You may consult Vishay Sfernice for chip sizes, ohmic

values and tolerances outside of the qualified range.

POWER DERATING CURVE

RATED POWER (W)

0.500

2010

PACKAGING

Two types of packaging are available: Waffle-pack and tape

and reel.

NUMBER OF PIECES PER PACKAGE

SIZE

WAFFLE

PACK

2" × 2"

100

140

TAPE AND REEL

(2)

MIN.

MAX.

5000

4000

1000

8 mm

TAPE

WIDTH

0.250

1206

0402

0603

0805

1206

2010

0.125

0.100

0.050

0805

0603

0402

155

AMBIENT TEMPERATURE (°C)

Note

(2)

MoQ: 50 pieces

Revision: 03-Jan-2019

Document Number: 53037

For technical questions, contact:

sferthinfilm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

PHR

www.vishay.com

Vishay Sfernice

REQUIREMENTS

ESA/SCC 4001/023

± 0.05 % + (0.05



x 100/Rn)

± 0.05 % + (0.05



x 100/Rn)

± 0.05 % + (0.05



x 100/Rn)

MIL-PRF-55342G

0.10 %

0.1 %

(for 100 cycles)

PERFORMANCE

TEST

Short time overload

Rapid temperature



change

Soldering



(thermal shock)

Terminal strength:

adhesion bend strength



of end plated facing

Climatic sequence

Load life

High temperature exposure

CONDITIONS



6.25 Pn x Rn



max.

< 2 UL - 2 s

-55 °C / +155 °C 5 cycles

CEI 66-2-14 Test Na

260 °C / 10 s

CEI 68-2-20 A Test T6

(met. 1A)

CEI 115-1 Clause 4.32

CEI 115-1 Clause 4.33

CEI 67-2-1 / CEI 68-2-2

CEI 67-2-13 / CEI 68-2-30

2000 h Pn at +70 °C

90’ / 30’ cycle

2000 h Pn at +155 °C

CEI 68-2-20A Test B

TYPICAL

± 0.01 %

± 0.015 % (for 500 cycles)

± 0.005 %

± 0.05 % + (0.05



x 100/Rn)

± 0.10 % + (0.05



x 100/Rn)

± 0.15 % + (0.05



x 100/Rn)

± 0.15 % + (0.05



x 100/Rn)

0.5 %

± 0.10 %

(duration 1000 h)

± 0.01 %

± 0.02 %

Insulation resistance > 1 G

± 0.02 %

Insulation resistance > 1 G

± 0.05 %

Insulation resistance > 1 G

ESCC/PHR CODIFICATION CORRESPONDENCE TABLES

VARIANT

PHR

MODEL

CASE SIZE

0402

0603

0805

1206

2010

0402

0603

0805

1206

2010

G (gold)

B (tin/lead)

TERMINATION

ESCC/PHR CODIFICATION CORRESPONDENCE TABLES

TEMPERATURE COEFFICIENT

5 ppm/°C (+22 °C; +70 °C)

10 ppm/°C (-55 °C; +155 °C)

25 ppm/°C (-55 °C; +155 °C)

5 ppm/°C (-55 °C; +155 °C)

ESCC CODE

PHR CODE

ESCC/PHR CODIFICATION CORRESPONDENCE TABLES

TOLERANCE

0.1 %

0.05 %

0.02 %

0.01 %

ESCC CODE

PHR CODE

Revision: 03-Jan-2019

Document Number: 53037

For technical questions, contact:

sferthinfilm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

PHR

www.vishay.com

Vishay Sfernice

GLOBAL PART NUMBER INFORMATION

LIMITED TO 18 DIGITS: If more digits are necessary a codification of some digits might be necessary

TYPE

PHR0402

PHR0603

PHR0805

PHR1206

PHR2010

TCR

PACKAGING

For more

information

see

Codification

of Packaging

table

OPTION

Leave

blank

if no

option

= ± 10 ppm/°C

= ± 25 ppm/°C

= 5 ppm/°C

(+22 °C; +70 °C)

= 5 ppm/°C

(-55 °C; +155 °C)

OHMIC

VALUE

The first three digits are

significant figures and the

last digit specifies the

number of zero to follow. R

designates decimal point.

Example:

10R0

= 10



3901

= 3900



1004

= 1 M

TOLERANCE

= ± 0.01 %

= ± 0.02 %

= ± 0.05 %

= ± 0.10 %

TERMINATION

SnPb over

nickel barrier

gold

Note

•

Terminations B:

Variants 01 / 02 / 03 / 04 and 13

Terminations G:

Variants 05 / 06 / 07 / 08 and 14

GLOBAL PART NUMBER INFORMATION

ESCC Code

ESCC SPEC

4001023

VARIANT

TCR

= 0402

= 0603

= 0805

= 1206

= 2010

OHMIC

VALUE

The first three digits are

significant figures and the

last digit specifies the

number of zero to follow. R

designates decimal point.

Example:

10R0

= 10



3901

= 3900



1004

= 1 M

TOLERANCE

= ± 0.01 %

= ± 0.02 %

= ± 0.05 %

= ± 0.10 %

= ± 10 ppm/°C

= ± 5 ppm/°C

(+22 °C; +70 °C)

= ± 25 ppm/°C

= ± 5 ppm/°C

(-55 °C; +155 °C)

CODIFICATION PACKAGING

- Waffle Pack

CODE 18

PACKAGING

25 min. (100 min. for size 0402), 1 mult

100 min., 100 mult

(1)

CODIFICATION PACKAGING

- Paper Tape

(2)

CODE 18

(3)

PACKAGING

100 min., 1 mult

100 min., 100 mult

250 min., 250 mult

500 min., 500 mult

1000 min., 1000 mult

2500 min., 2500 mult

Full tape

CODIFICATION PACKAGING

- Plastic Tape

(2)

CODE 18

PACKAGING

50 min. (100 min. for size 0402), 1 mult

100 min., 100 mult

250 min., 250 mult

500 min., 500 mult

1000 min., 1000 mult

2500 min., 2500 mult

Full tape

(3)

(1)

(3)(4)

Notes

Available only in size 1206

(2)

Plastic tape in standard for all sizes. Paper tape in option for

0402, 0603, 0805 and 1206. Please consult Vishay Sfernice for

2010 size

(3)

Not available for size 0402

(4)

Qantity depending on size of chips

Revision: 03-Jan-2019

Document Number: 53037

For technical questions, contact:

sferthinfilm@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

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