1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
AD7492
FEATURES
Specified for V
DD
of 2.7 V to 5.25 V
Throughput rate of 1 MSPS (AD7492)
Throughput rate of 1.25 MSPS (AD7492-5)
Throughput rate of 400 kSPS (AD7492-4)
Low power
4 mW typ at 1 MSPS with 3 V supplies
11 mW typ at 1 MSPS with 5 V supplies
Wide input bandwidth
70 dB typ SNR at 100 kHz input frequency
2.5 V internal reference
On-chip CLK oscillator
Flexible power/throughput rate management
No pipeline delays
High speed parallel interface
Sleep mode: 50
n
A typ
24-lead SOIC and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
AV
DD
4
DV
DD
20
REF OUT
5
V
DRIVE
21
2.5V
REF
BUF
CLOCK
OSCILLATOR
V
IN 6
T/H
12-BIT SAR
ADC
OUTPUT
DRIVERS
DB11
DB0
11
PS/FS
CS
RD
BUSY
01128-001
CONVST
10
CONTROL
LOGIC
8
9
AD7492
12
7
19
AGND
DGND
Figure 1.
GENERAL DESCRIPTION
The AD7492, AD7492-4, and AD7492-5 are 12-bit high speed,
low power, successive approximation ADCs. The parts operate
from a single 2.7 V to 5.25 V power supply and feature
throughput rates up to 1.25 MSPS. They contain a low noise,
wide bandwidth track/hold amplifier that can handle
bandwidths up to 10 MHz.
The conversion process and data acquisition are controlled
using standard control inputs allowing for easy interface to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CONVST and conversion is also initiated at this
point. The BUSY pin goes high at the start of conversion and
goes low 880 ns (AD7492/AD7492-4) or 680 ns (AD7492-5)
later to indicate that the conversion is complete. There are no
pipeline delays associated with the part. The conversion result is
accessed via standard CS and RD signals over a high speed
parallel interface.
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The type of sleep mode is hardware selected by the PS/FS pin.
Using these sleep modes allows very low power dissipation
numbers at lower throughput rates.
The analog input range for the part is 0 V to REFIN. The
2.5 V reference is supplied internally and is available for
external referencing. The conversion rate is determined by the
internal clock.
PRODUCT HIGHLIGHTS
1.
High Throughput with Low Power Consumption. The
AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.
Flexible Power/Throughput Rate Management. The
conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to
maximize power efficiency at lower throughput rates.
No Pipeline Delay. The part features a standard successive
approximation ADC with accurate control of the sampling
instant via a CONVST input and once-off conversion
control.
Flexible Digital Interface. The V
DRIVE
feature controls the
voltage levels on the I/O digital pins.
Fewer Peripheral Components. The AD7492 optimizes
PCB space by using an internal reference and internal CLK.
2.
3.
4.
5.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD7492
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ....................................................................... 1
Revision History ........................................................................... 2
Specifications..................................................................................... 3
AD7492-5 ...................................................................................... 3
AD7492/AD7492-4 ...................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Peformance Characteristics ............................................. 10
Terminology .................................................................................... 12
Circuit Description......................................................................... 13
Converter Operation.................................................................. 13
Typical Connection Diagram ................................................... 13
ADC Transfer Function............................................................. 13
AC Acquisition Time ................................................................. 14
DC Acquisition Time................................................................. 14
Analog Input ............................................................................... 14
Parallel Interface......................................................................... 14
Operating Modes........................................................................ 14
Power-Up..................................................................................... 16
Grounding and Layout .............................................................. 18
Power Supplies ............................................................................ 18
Microprocessor Interfacing....................................................... 18
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
5/06—Rev. 0 to Rev. A
Added AD7492-4................................................................Universal
Changes to Table 4............................................................................ 8
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
1/01—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7492
SPECIFICATIONS
AD7492-5
V
DD
= 4.75 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
A Version
1
69
68
70
68
−83
−87
−75
−83
−90
−76
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
Input High Voltage, V
INH 2
Input Low Voltage, V
INL2
Input Current, I
IN
Input Capacitance, C
IN 3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
−82
−90
−71
−88
5
15
10
12
±1.5
+1.5/–0.9
±9
±2.5
0 to 2.5
±1
33
2.5
V
DRIVE
× 0.7
V
DRIVE
× 0.3
±1
10
V
DRIVE
− 0.2
0.4
±10
10
Straight (natural)
binary
B Version
1
69
68
70
68
−83
−87
−75
−83
−90
−76
−82
−90
−71
−88
5
15
10
12
±1.25
+1.5/−0.9
±9
±2.5
0 to 2.5
±1
33
2.5
V
DRIVE
× 0.7
V
DRIVE
× 0.3
±1
10
V
DRIVE
− 0.2
0.4
±10
10
Straight (natural)
binary
Unit
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
μA max
pF typ
V
V min
V max
μA max
pF max
V min
V max
μA max
pF max
±1.5% for specified performance
V
DD
= 5 V ± 5%
V
DD
= 5 V ± 5%
Typically 10 nA, V
IN
= 0 V or V
DD
Test Conditions/Comments
f
S
= 1.25 MSPS
f
IN
= 500 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
f
IN
= 100 kHz sine wave
Peak Harmonic or Spurious-Free
Dynamic Noise (SFDR)
f
S
= 1.25 MSPS
Guaranteed no missed codes to
12 bits (A and B versions)
I
SOURCE
= 200 μA
I
SINK
= 200 μA
Rev. A | Page 3 of 24
AD7492
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation
4
Normal Mode
Partial Sleep Mode
Full Sleep Mode
1
2
A Version
1
680
120
1.25
B Version
1
680
120
1.25
Unit
ns max
ns min
MSPS max
Test Conditions/Comments
Conversion time + acquisition
time
4.75/5.25
3.3
1.8
250
1
16.5
1.25
5
4.75/5.25
3.3
1.8
250
1
16.5
1.25
5
V min/max
mA max
mA max
μA max
μA max
mW max
mW max
μW max
Digital I/Ps = 0 V or DV
DD
f
S
= 1.25 MSPS, typ 2.75 mA
Static, typ 190 μA
Static, typ 200 nA
Digital I/Ps = 0 V or DV
DD
Temperature ranges as follows: A and B Versions: −40°C to +85°C.
V
INH
and V
INL
trigger levels are set by the V
DRIVE
voltage. The logic interface circuitry is powered by V
DRIVE
.
3
Sample tested @ 25°C to ensure compliance.
4
See the Power vs. Throughput section.
AD7492/AD7492-4
V
DD
= 2.7 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
A Version
2
B Version
2
Unit
Test Conditions/Comments
f
S
= 1 MSPS for AD7492
f
S
= 400 kSPS for AD7492-4
f
IN
= 500 kHz sine wave
3
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
3
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
3
f
IN
= 100 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
3
f
IN
= 100 kHz sine wave
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
3
f
IN
= 100 kHz sine wave
f
IN
= 500 kHz sine wave
3
f
IN
= 100 kHz sine wave
Peak Harmonic or Spurious-Free
Dynamic Noise (SFDR)
69
68
70
68
−85
−87
−75
−86
−90
−76
69
68
70
68
−85
−87
−75
−86
−90
−76
−77
−90
−69
−88
5
15
10
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
Intermodulation Distortion (IMD)
Second Order Terms
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
−77
−90
−69
−88
5
15
10
Rev. A | Page 4 of 24
AD7492
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity
A Version
2
B Version
2
Unit
Test Conditions/Comments
f
S
= 1 MSPS for AD7492
f
S
= 400 kSPS for AD7492-4
12
±1.5
12
±0.6
±1
+1.5/−0.9
±9
±2.5
0 to 2.5
±1
33
2.5
V
DRIVE
× 0.7
V
DRIVE
× 0.3
±1
10
V
DRIVE
− 0.2
0.4
±10
10
Straight (Natural)
Binary
880
120
1
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
Input High Voltage, V
INH 4
Input Low Voltage, V
INL4
Input Current, I
IN
Input Capacitance, C
IN3, 5
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
+1.5/−0.9
±9
±2.5
0 to 2.5
±1
33
2.5
V
DRIVE
× 0.7
V
DRIVE
× 0.3
±1
10
V
DRIVE
− 0.2
0.4
±10
10
Straight (Natural)
Binary
880
120
1
400
Bits
LSB max
LSB typ
LSB max
LSB max
LSB max
LSB max
V
μA max
pF typ
V
V min
V max
μA max
pF max
V min
V max
μA max
pF max
V
DD
= 5 V
V
DD
= 3 V
Guaranteed no missed codes to
12 bits (A and B versions)
±1.5% for specified performance
V
DD
= 5 V ± 5%
V
DD
= 5 V ± 5%
Typically 10 nA, V
IN
= 0 V or V
DD
I
SOURCE
= 200 μA
I
SINK
= 200 μA
ns max
ns min
MSPS max
kSPS max
Conversion time + acquisition
time for AD7492
Conversion time + acquisition
time for AD7492-4
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode
2.7/5.25
3
2.7/5.25
3
V min/max
mA max
Digital I/Ps = 0 V or DV
DD
.
f
S
= 1 MSPS, typ 2.2 mA
f
S
= 400 kSPS, Typ 2.2 mA
(AD7492-4)
Static, typ 190 μA
Static, typ 200 nA
Digital I/Ps = 0 V or DV
DD
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation
4, 6
Normal Mode
Partial Sleep Mode
Full Sleep Mode
1
2
1.8
250
1
15
1.25
5
1.8
250
1
15
1.25
5
mA max
μA max
μA max
mW max
mW max
μW max
Only A version specification applies to the AD7492-4.
Temperature ranges as follows: A and B versions: −40°C to +85°C.
3
500 kHz sine wave specifications do not apply for the AD7492-4.
4
V
INH
and V
INL
trigger levels are set by the V
DRIVE
voltage. The logic interface circuitry is powered by V
DRIVE
.
5
Sample tested @ 25°C to ensure compliance.
6
See the Power vs. Throughput section.
Rev. A | Page 5 of 24
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