Philips Semiconductors
Product specification
Programmable ripple counter with
oscillator; 3-state
FEATURES
•
8-pin space saving package
•
Programmable 3-stage ripple
counter
•
Suitable for over-tone crystal
application up to 50 MHz
(V
CC
= 5 V
±
10%)
•
3-state output buffer
•
Two internal capacitors
•
Recommended operating range for
use with third overtone crystals
3 to 6 V
•
Oscillator stop function (MR)
•
Output capability:
bus driver
→
(15 LSTTL)
•
I
CC
category: MSI.
APPLICATIONS
•
Control counters
•
Timers
•
Frequency dividers
•
Time-delay circuits
•
CIO (Compact Integrated
Oscillator)
•
Third-overtone crystal operation.
Notes
GENERAL DESCRIPTION
The HC/HCT6323A are high-speed
Si-gate CMOS devices.
They are specified in compliance with
JEDEC standard no. 7A.
The HC/HCT6323A are oscillators
designed for quartz crystal combined
with a programmable 3-state counter,
a 3-state output buffer and an
overriding asynchronous master
reset (MR). With the two select inputs
S1 and S2 the counter can be
switched in the divide-by-1, 2, 4 or 8
mode. If left floating the clock is
divided by 8. The oscillator is
designed to operate either in the
fundamental or third overtone mode
depending on the crystal and external
components applied. On-chip
September 1993
C
PD
SYMBOL
t
PHL
/t
PLH
PARAMETER
propagation delay
X1 to OUT
(S1 = S2 = LOW)
maximum clock
frequency
input capacitance
except X1 and X2
power dissipation
capacitance per
package
capacitors minimize external
component count for third overtone
crystal applications.
The oscillator may be replaced by an
external clock signal at input X1. In
this event the other oscillator pin (X2)
must be floating. The counter
advances on the negative-going
transition of X1. A LOW level on MR
resets the counter, stops the oscillator
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
74HC/HCT6323A
and sets the output buffer in the
3-state condition. MR can be left
floating since an internal pull-up
resistor will make the MR inactive. In
the HCT version, the MR input and
the two mode select pins S1 and S2
are TTL compatible, but the X1 input
has CMOS input switching levels and
may be driven by a TTL output using
a pull-up resistor connected to V
CC
.
TYP.
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V
17
HCT
17
ns
UNIT
f
max
C
I
90
3.5
+1; notes 1 and 2
+2; notes 1 and 2
+4; notes 1 and 2
+8; notes 1 and 2
54
42
36
33
90
3.5
54
42
36
33
MHz
pF
pF
pF
pF
pF
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= (C
PD
x V
CC2
x f
i
) + (C
L
+ V
CC2
x f
o
) + (I
pull-up
x V
CC
)
where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz.
V
CC
= supply voltage in V; C
L
= output load capacitance in pF.
I
pull-up
= pull-up currents in
µA.
2. For HC and HCT an external clock is applied to X1 with:
t
r
= t
f
≤
6 ns, V
i
is GND to V
CC
, MR = HIGH
I
pull-up
is the summation of
−I
I
(µA) of S1 and S2 inputs at the LOW state.
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
74HC/HCT6323AD
PACKAGE
PINS
8
PIN POSITION
SO
MATERIAL
plastic
CODE
SOT96
2
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