DISCRETE SEMICONDUCTORS
DATA SHEET
BSP254; BSP254A
P-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching
•
No secondary breakdown.
DESCRIPTION
P-channel vertical D-MOS transistor
in a TO-92 variant envelope and
intended for use as a line current
interruptor in relay, high-speed and
line transformer drivers.
PINNING - TO-92 variant BSP254
PIN
1
2
3
gate
drain
source
handbook, halfpage
BSP254; BSP254A
QUICK REFERENCE DATA
SYMBOL
V
DS
V
GSO
Y
fs
I
D
R
DS(on)
P
tot
PARAMETER
drain-source
voltage
gate-source
voltage
forward transfer
admittance
drain current (DC)
drain-source
V
GS
=
−10
V;
on-state resistance I
D
=
−200
mA
total power
dissipation
T
amb
= 25
°C
open drain
I
D
=
−200
mA;
V
DS
=
−25V
CONDITIONS MIN. TYP. MAX. UNIT
−
−
100
−
−
−
−
−
200
−
10
−
−250
±20
−
−0.2
15
1
V
V
mS
A
Ω
W
DESCRIPTION
d
1
2
3
g
PINNING - TO-92 variant BSP254A
MAM147
s
PIN
1
2
3
gate
drain
DESCRIPTION
source
Fig.1 Simplified outline and symbol.
April 1995
2
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134)
SYMBOL
−V
DS
V
GSO
BSP254; BSP254A
PARAMETER
drain-source voltage
gate-source voltage
drain current
drain current
total power dissipation
storage temperature range
junction temperature
CONDITIONS
−
open drain
DC
peak value
T
amb
= 25
°C
(note 1)
−
−
−
−
MIN.
MAX.
250
20
0.2
0.6
1
+150
150
V
V
A
A
UNIT
−I
D
−I
DM
P
tot
T
stg
T
j
W
°C
°C
−65
−
THERMAL RESISTANCE
SYMBOL
R
th j-a
Note
1. Transistor mounted on printed circuit board, maximum lead length 4 mm,
mounting pad for drain lead minimum 10 mm x 10 mm.
PARAMETER
from junction to ambient (note 1)
MAX.
125
UNIT
K/W
handbook, halfpage
1.2
MRC238
Ptot
(W)
0.8
0.4
0
0
50
100
150
200
Tamb (°C)
Fig.2 Power derating curve.
April 1995
3
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
−V
(BR)DSS
−I
DSS
±I
GSS
−V
GS(th)
R
DS(on)
Y
fs
C
iss
C
oss
C
rss
t
on
t
off
Notes
1. Measured at f = 1 MHz;
−V
DS
= 25 V; V
GS
= 0.
2.
−V
GS
= 0 to 10 V;
−I
D
= 250 mA;
−V
DD
= 50 V.
PARAMETER
drain-source breakdown voltage
drain-source leakage current
gate-source leakage current
gate-source threshold voltage
drain-source on-resistance
transfer admittance
input capacitance
output capacitance
feedback capacitance
turn-on time
turn-off time
CONDITIONS
−V
GS
= 0
−I
D
= 10
µA
−V
DS
= 200 V
V
GS
= 0
±V
GS
= 20 V
V
DS
= 0
V
GS
= V
DS
−I
D
= 1 mA
−V
GS
= 10 V
−I
D
= 200 mA;
−V
DS
= 25 V
−I
D
= 200 mA
note 1
note 1
note 1
note 2
note 2
BSP254; BSP254A
MIN.
250
−
−
0.8
−
100
−
−
−
−
−
TYP.
−
−
−
−
10
200
65
20
6
5
20
MAX.
−
1
100
2.8
15
−
90
30
15
10
30
UNIT
V
µA
nA
V
Ω
mS
pF
pF
pF
ns
ns
handbook, halfpage
VDD =
−50
V
handbook, halfpage
10 %
INPUT
90 %
0V
−10
V
ID
50
Ω
MBB689
10 %
OUTPUT
90 %
ton
toff
MBB690
Fig.3 Switching times test circuit.
Fig.4 Input and output waveforms.
April 1995
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BSP254; BSP254A
handbook, halfpage
−1
MDA706
ID
VGS =
−10
V
−6
V
handbook, halfpage
−1
MDA707
(A)
−0.8
ID
(A)
−0.8
−0.6
−5
V
−0.6
−0.4
−4
V
−0.2
−3
V
0
0
−5
−10
−15
−20
−25
VDS (V)
−0.4
−0.2
0
0
−2
−4
−6
−8
−10
VGS (V)
Fig.5 Typical output characteristics; T
j
= 25
°C.
Fig.6
Typical transfer characteristic; V
DS
=
−10
V;
T
j
= 25
°C.
handbook, halfpage
−10
3
MDA708
VGS =
−10
V
−5
V
handbook, halfpage
160
MDA734
C
(pF)
120
ID
(mA)
−4
V
−10
2
80
Ciss
40
Coss
Crss
−10
0
8
12
16
20
24
28
RDSon (Ω)
0
−5
−10
−15
−20
−25
VDS (V)
Fig.7
Typical on-resistance as a function of drain
current, T
j
= 25
°C.
Fig.8
Typical capacitances as a function of
drain-source voltage; V
GS
= 0; f = 1 MHz;
T
j
= 25
°C.
April 1995
5
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