BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
1M x 16 or 2M x 8 bit switchable
BS616LV1622
• Wide Vcc operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 45mA (@55ns) operating current
I -grade: 46mA (@55ns) operating current
C-grade: 36mA (@70ns) operating current
I -grade: 37mA (@70ns) operating current
3.0uA (Typ.)
CMOS standby current
Vcc = 5.0V C-grade: 113mA (@55ns) operating current
I -grade: 115mA (@55ns) operating current
C-grade: 90mA (@70ns) operating current
I -grade: 92mA (@70ns) operating current
15uA (Typ.)
CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
DESCRIPTION
The BS616LV1622 is a high performance, very low power CMOS Static
Random Access Memory organized as 1,048,676 words by 16 bits or
2,097,152 bytes by 8 bits selectable by CIO pin and operates in a wide
range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of
3.0uA
at 3V/25
o
C and maximum access time of 55ns at 3.0V/85
o
C .
This device provide three control inputs and three states output drivers
for easy memory expansion.
The BS616LV1622 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1622 is available in 48-pin 12mmx20mm TSOP1 package.
PRODUCT FAMILY
PRODUCT FAMILY
OPERATING
TEMPERATURE
+0 C to +70 C
-40
O
C to +85
O
C
O
O
Vcc
RANGE
2.4V ~ 5.5V
2.4V ~ 5.5V
SPEED
(ns)
55ns : 3.0~5.5V
70ns : 2.7~5.5V
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=3V
Vcc=5V
Vcc=3V
70ns
Vcc=5V
70ns
BS616LV1622TC
BS616LV1622TI
55 / 70
55 / 70
10uA
20uA
110uA
220uA
36mA
37mA
90mA
92mA
TSOP1-48
(12mmx20mm)
TSOP1-48
(12mmx20mm)
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
/CE1
D0
D1
D2
D3
Vcc
CIO
Vss
D4
D5
D6
D7
A19
/WE
A18
A17
A16
A15
A14
1
48
47
46
A5
A6
A7
/OE
/UB
/LB
CE2
SAE
D15
D14
D13
D12
Vss
Vcc
D11
D10
D9
D8
A8
A9
A10
A11
A12
A13
BLOCK DIAGRAM
A19
A15
A14
A13
A12
A11
A10
A9
A8
A17
A7
A6
Address
Input
Buffer
24
Row
Decoder
4096
Memory Array
4096 x 4096
9
10
13
BS616LV1622TC
BS616LV1622T I
37
4096
D0
16(8)
Data
Input
Buffer
16(8)
Column I/O
16
17
.
.
.
.
D15
CE1
CE2
WE
OE
UB
.
.
.
.
Write Driver
16(8)
Sense Amp
256(512)
Column Decoder
16(8)
Data
Output
Buffer
27
24
25
16(18)
Control
Address Input Buffer
48-pin 12mmx20mm TSOP1 top view
LB
CIO
Vdd
Vss
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
R0201-BS616LV1622
1
Revision 2.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS616LV1622
Name
A0-A19 Address Input
SAE Address Input
CIO x8/x16 select input
Function
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
This address input incorporates with the above 20 address inputs select one of the
2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
This input selects the organization of the SRAM. 1,048,576 x 16-bit words
configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is
selected if CIO is LOW.
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Vcc
Gnd
R0201-BS616LV1622
2
Revision 2.1
Jan.
2004
BSI
TRUTH TABLE
MODE
CE1
H
Fully Standby
X
Output Disable
L
L
H
H
H
X
CE2
X
X
X
X
X
X
L
Read from SRAM
( WORD mode )
L
H
L
H
H
H
L
L
Write to SRAM
( WORD mode )
L
H
X
L
H
H
L
Read from SRAM
( BYTE Mode )
Write to SRAM
( BYTE Mode )
L
H
L
H
L
X
X
X
H
L
L
H
L
L
X
A-1
X
X
X
OE
WE
CIO
LB
X
UB
X
X
SAE
BS616LV1622
D0~7
D8~15
VCC Current
High-Z
High-Z
I
CCSB
, I
CCSB1
High-Z
Dout
High-Z
Dout
Din
X
Din
Dout
High-Z
High-Z
Dout
Dout
X
Din
Din
High-Z
I
CC
I
CC
I
CC
I
CC
L
H
X
L
L
X
X
A-1
Din
X
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
OPERATING RANGE
UNITS
V
O
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0 C to +70 C
-40
O
C to +85
O
C
O
O
Vcc
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
10
12
pF
pF
1. This parameter is guaranteed and not 100% tested.
R0201-BS616LV1622
3
Revision 2.1
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = -40
o
C to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(4)
BS616LV1622
PARAMETER
Guaranteed Input Low
Voltage
(3)
Guaranteed Input High
Voltage
(3)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
TEST CONDITIONS
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
MIN. TYP.
-0.5
-0.5
--
(1)
MAX.
0.8
0.8
Vcc+0.3
Vcc+0.3
1
1
0.4
0.4
--
--
37
92
1.3
2.5
20
UNITS
2.0
2.2
--
--
--
--
2.4
2.4
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
3
15
V
V
uA
uA
V
V
mA
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE1 = V
IH
, or CE2 =
V
iL
, or
OE = V
IH
, V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2mA
Vcc = Min, I
OH
= -1mA
CE1 = V
IL
and CE2 = V
IH
, I
DQ
= 0mA, F = Fmax
(2)
CE1 = V
IH
or CE2 = V
IL
, I
DQ
= 0mA
CE1
≧
Vcc-0.2V, or CE2
≦
0.2V, or
LB and UB
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
70ns
70ns
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
Vcc=3V
Vcc=5V
I
CCSB
I
CCSB1
(5)
Standby Current-CMOS
uA
220
1. Typical characteristics are at TA = 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
5.I
cc
s
B1
is
10uA/110uA
at Vcc=3.0V/5.0V and T
A
=70
o
C.
4. Icc
_Max.
is 46mA(@3.0V) / 115mA(@5.0V) under 55ns operation.
R0201-BS616LV1622
4
Revision 2.1
Jan.
2004
BSI
DATA RETENTION CHARACTERISTICS
( TA = -40
o
C to +85
o
C )
SYMBOL
V
DR
BS616LV1622
TEST CONDITIONS
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V or
LB
≧
Vcc - 0.2V and UB
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE1
≧
Vcc - 0.2V or CE2
≦
0.2V or
LB
≧
Vcc - 0.2V and UB
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
PARAMETER
Vcc for Data Retention
MIN.
1.5
TYP.
(1)
--
MAX.
--
UNITS
V
(3)
I
CCDR
Data Retention Current
Chip Deselect to Data
Retention Time
--
1.5
5
uA
t
CDR
t
R
0
See Retention Waveform
T
RC
(2)
--
--
--
--
ns
ns
Operation Recovery Time
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
(Max.) is
2.5uA
at T
A
=70
O
C.
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
Data Retention Mode
Vcc
V
IH
Vcc
V
DR
≧
1.5V
Vcc
t
CDR
CE1
≧
Vcc - 0.2V
t
R
V
IH
CE1
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
V
DR
≧
1.5V
Vcc
t
CDR
t
R
CE2
≦
0.2V
CE2
V
IL
V
IL
R0201-BS616LV1622
5
Revision 2.1
Jan.
2004
Analog electronics
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