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XC25BS3021MR

Description
Clock Generator
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size263KB,12 Pages
ManufacturerTOREX
Websitehttp://www.torex.co.jp/chinese/
Environmental Compliance
Download Datasheet Parametric View All

XC25BS3021MR Overview

Clock Generator

XC25BS3021MR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid110291586
Reach Compliance Codeunknown
ECCN codeEAR99
XC25BS3
Series
PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits
ETR1501_004a
■GENERAL
DESCRIPTION
The XC25BS3 series are high frequency, low power consumption PLL clock generator ICs with built-in crystal oscillator circuit,
divider circuit & multiplier PLL circuit.
Laser trimming gives the option of being able to select from divider ratios (M) of 1 to 2047 and multiplier ratio (N) of 20 to
2047. Output frequency (Q0) is equal to reference oscillation (fCLKin) multiplied by N/M, within a range of 9MHz to 80MHz.
Q1 output is selectable from input reference frequency (f0), Ground (GND), PLL output frequency/2 (Q0/2), and comparative
frequency/2 (f0/M/2). Reference oscillation can input 14kHz to 35MHz of reference clock. Further, comparative frequency,
within a range of 14kHz to 500kHz, can be obtained by dividing the reference oscillation. By halting oscillation via the CE
pin, consumption current can be controlled.
Output will be one of high impedance.
■APPLICATIONS
●Crystal
oscillation modules
●Microcontroller
●PDAs
●Portable
audio systems
●Various
system clocks
■FEATURES
Output Frequency
Input Frequency
(fCLKin)
Divider Ratio (M)
Multiplier Ratio (N)
Output
: Selectable from divisions of 1 ~ 2047
: Selectable from multiplications of 20 ~ 2047
: 3-State
Q1 output selectable from
reference oscillation, GND, PLL
output frequency/2, comparative
frequency/2.
Operating Voltage Range
: 2.97V ~ 5.5V
Low Power Consumption
: CMOS (stand-by function included)*1
Comparative Frequency
: 14kHz ~ 500kHz
Ultra Small Package
: SOT-26, USP-6B
Environmentally Friendly
: EU RoHS Compliant, Pb Free
*1 High output impedance during stand-by
: 9MHz ~ 80MHz (Q0=fCLKin×N/M)
: 14kHz ~ 35MHz
■PIN
CONFIGURATION
Q1
VDD
CLKin
SOT-26
(TOP VIEW)
■PIN
ASSIGNMENT
PIN NUMBER
Q0
VSS
CE
SOT-26 USP-6B
1
2
3
3
2
1
6
5
4
PIN NAME
CE
V
SS
Q0
Q1
V
DD
CLKin
FUNCTION
Chip Enable
GND
PLL Output
Reference Oscillation, GND,
Comparative Frequency/2,
or PLL Output/2 Output *
Power Supply
Reference Clock Input
*The dissipation pad for the USP-6B
package should be solder-plated in
recommended mount pattern and metal
masking so as to enhance mounting
strength and heat release.
If the pad needs to be connected to other
pins, it should be connected to the V
DD
pin.
4
5
6
* Q1 Output is selectable from the above mentioned functions.
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