®
SP706P/R/S/T, SP708R/S/T
+3.0V/+3.3V Low Power Microprocessor
Supervisory Circuits
■
Precision Low Voltage Monitor:
SP706P/R
and
SP708R
at +2.63V
SP706S
and
SP708S
at +2.93V
SP706T
and
SP708T
at +3.08V
■
RESET Pulse Width - 200ms
■
Independent Watchdog Timer - 1.6 sec
Timeout (SP706P/S/R/T)
■
40µA Maximum Supply Current
■
Debounced TTL/CMOS Manual-Reset Input
■
RESET Asserted Down to V
CC
= 1V
■
RESET Output:
SP706P
Active-High
SP706R/S/T
Active-Low
SP708R/S/T
Both Active High + Active Low
■
WDI Can Be Left Floating, Disabling the
Watchdog Function
Now Available in Lead Free Packaging
■
Built-In V
cc
Glitch Immunity
■
Available in 8-pin PDIP, NSOIC, and
µSOIC
packages
■
Voltage Monitor for Power Failure or Low
Battery Warning
■
Pin Compatible Enhancement to Industry
Standards
706P/R/S/T
and
708R/S/T
The SP706P/S/R/T, SP708R/S/T series is a family of microprocessor (µP) supervisory circuits
that integrate myriad components involved in discrete solutions which monitor power-supply and
battery, in
µP,
and digital systems. The SP706P/S/R/T, SP708R/S/T series will significantly
improve system reliability and operational efficiency when compared to results obtained with
discrete components. The features of the SP706P/S/R/T, SP708R/S/T series include a
watchdog timer, a
µP
reset, a Power Fail Comparator, and a manual-reset input. The SP706P/
S/R/T, SP708R/S/T series is ideal for +3.0V or +3.3V applications in automotive systems,
computers, controllers, and intelligent instruments. The SP706P/S/R/T, SP708R/S/T series is
an ideal solution for systems in which critical monitoring of the power supply to the
µP
and related
digital components is demanded.
Part Number
SP706P
SP706R
SP706S
SP706T
SP708R
SP708S
SP708T
Date: 6-28-04
RESET Active
HIGH
LOW
LOW
LOW
LOW/HIGH
LOW/HIGH
LOW/HIGH
RESET Threshold
2.63V
2.63V
2.93V
3.08V
2.63V
2.93V
3.08V
Manual Reset
YES
YES
YES
YES
YES
YES
YES
PFI Accuracy
4%
4%
4%
4%
4%
4%
4%
Watchdog Input
YES
YES
YES
YES
NO
NO
NO
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
© Copyright 2004 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability.
Terminal Voltage (with respect to GND):
V
CC
........................................................-0.3V to +6.0V
All Other Inputs ...........................-0.3V to (V
CC
+3.0V)
Input Current:
V
CC
.....................................................................20mA
GND...................................................................20mA
Output Current (all outputs)...............................20mA
ESD Rating...........................................................2kV
Continuous Power Dissipation
Plastic DIP
(derate 9.09mW/
O
C above +70
O
C)..................727mW
SO
(derate 5.88mW/
O
C above +70
O
C)..................471mW
Mini SO
(derate 4.10mW/
O
C above +70
O
C)..................330mW
Storage Temperature Range.............-65˚C to +160˚C
Lead Temperature (solding 10 sec)................+300˚C
SPECIFICATIONS
V
cc
= 2.7V to 5.5V for SP70_P/R, V
CC
= 3.0 to 5.5V for SP70_S, V
CC
= 3.15V to 5.5V for SP70_T, T
A
= T
MIN
to T
MAX
to T
MAX
, unless otherwise noted,
typical at 25°C.
PARAMETER
Operating Voltage Range, V
CC
Supply Current, I
SUPPLY
Reset Threshold
MIN.
1.0
TYP.
MAX.
5.5
40
2.70
3.00
3.15
280
UNITS
V
µA
V
mV
ms
CONDITIONS
2.55
2.85
3.00
140
0.8xV
CC
Reset Threshold Hysteresis
Reset Pulse Width, t
RS
RESET Output Voltage
V
OH
V
OL
V
OH
V
OL
RESET Output Voltage
V
OH
V
OL
V
OH
V
OL
Watchdog Timeout Period, t
WD
WDI Pulse Width, t
WP
(Note1)
WDI Input Threshold,
V
IL
V
IH
V
IL
V
IH
WDI Input Current
25
2.63
2.93
3.08
20
200
MR=V
CC
or Floating, WDI Floating
SP70_P/R
SP70_S
SP70_T
Note 2
Note 2
V
RST(MAX)
<V
CC
<3.6V, I
SOURCE
= 500
µA
V
RST(MAX)
<V
CC
<3.6V, I
SINK
=1.2mA
4.5V<V
CC
<5.5V, I
SOURCE
= 800
µA
4.5V<V
CC
<5.5V, I
SINK
= 3.2mA
V
RST(MAX)
<V
CC
<3.6V, I
SOURCE
= 215
µA
V
RST(MAX)
<V
CC
<3.6V, I
SOURCE
=1.2mA
4.5V<V
CC
<5.5V, I
SOURCE
= 800
µA
4.5V<V
CC
<5.5V, I
SOURCE
= 3.2mA
V
CC
<3.6V
V
IL
= 0.4V, V
IH
= 0.8xV
CC
V
RST (MAX)
<V
CC
<3.6V
V
RST (MAX)
<V
CC
<3.6V
V
CC
= 5.0V
V
CC
= 5.0V
WDI = 0 or V
CC
0.3
V
CC
-1.5
0.4
V
CC
-0.6
0.3
V
CC
-1.5
1.00
50
1.60
0.4
2.25
V
V
s
ns
0.6
0.7xV
CC
3.5
-1
V
0.8
0.02
1
µA
Note1: WDI Minimum Rise/Fall time is 1 microsecond.
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
© Copyright 2004 Sipex Corporation
2
SPECIFICATIONS (continued)
V
cc
= 2.7V to 5.5V for SP70_P/R, V
CC
= 3.0 to 5.5V for SP70_S, V
CC
= 3.15V to 5.5V for SP70_T, T
A
= T
MIN
to T
MAX
to T
MAX
, unless otherwise noted,
typical at 25°C.
PARAMETER
WDO Output Voltage
V
OH
V
OL
V
OH
V
OL
MR Pull-Up Current
MR Pulse Width, t
MR
MR Input Threshold
V
IL
V
IH
V
IL
V
IH
MR to Reset Out Delay, t
MD
PFI Input Threshold
PFI Input Current
PFO Output Voltage
V
OH
V
OL
V
OH
V
OL
MIN.
TYP.
MAX.
UNITS
CONDITIONS
0.8xV
CC
0.3
V
CC
-1.5
0.4
25
100
500
150
0.6
0.7xV
CC
2.0
750
250
1.20
-25.00
0.8xV
CC
V
CC
-1.5
1.25
0.01
1.30
25.00
ns
V
nA
V
0.8
70
250
250
600
µA
V
V
RST(MAX)
<V
CC
<3.6V, I
SOURCE
= 500
µA
V
RST(MAX)
<V
CC
<3.6V, I
SINK
=1.2mA
4.5V<V
CC
<5.5V, I
SOURCE
= 800
µA
4.5V<V
CC
<5.5V, I
SINK
= 3.2mA
MR = 0V,V
RST(MAX)
<V
CC
<3.6V
MR = 0V,4.5V<V
CC
<5.5V
V
RST(MAX)
<V
CC
<3.6V
4.5V<V
CC
<5.5V
V
RST(MAX)
<V
CC
<3.6V
V
RST(MAX)
<V
CC
<3.6V
4.5V<V
CC
<5.5V
4.5V<V
CC
<5.5V
V
RST(MAX)
<V
CC
<3.6V,NOTE 2
4.5V<V
CC
<5.5V,NOTE 2
V
CC
= 3.0V for the
SP70_P/R
,V
CC
=
3.3V for the
SP70_S/T
,PFI falling
ns
0.3
0.4
V
V
RST(MAX)
<V
CC
<3.6V, I
SOURCE
= 500
µA
V
RST(MAX)
<V
CC
<3.6V,I
SINK
=1.2mA
4.5V<V
CC
<5.5V, I
SOURCE
= 800
µA
4.5V<V
CC
<5.5V, I
SINK
= 3.2mA
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
© Copyright 2004 Sipex Corporation
3
DIP and SOIC
µSOIC
MR 1
V
CC
2
GND 3
PFI 4
SP706P/R/S/T
8
WDO
RESET / RESET* 1
WDO 2
MR 3
V
CC
4
SP706P/R/S/T
8
WDI
7 RESET / RESET*
6
5
WDI
PFO
7 PFO
6
5
PFI
GND
MR 1
V
CC
2
GND 3
PFI 4
SP708S/R/T
8
RESET
RESET 1
RESET 2
MR 3
V
CC
4
SP708S/R/T
8
N.C.
7 RESET
6
5
N.C.
PFO
*SP706P only
7 PFO
6
5
PFI
GND
*SP706P only
Figure 1. Pinouts
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
© Copyright 2004 Sipex Corporation
4
PIN DESCRIPTION
NAME
FUNCTION
SP706P
DIP/
SOIC
µSOIC
SP706R/S/T
DIP/
SOIC
µSOIC
SP708R/S/T
DIP/
SOIC
µSOIC
MR
Manual Reset - This input triggers a reset pulse
when pulled below 0.8V. This active-LOW input
has an internal 70
µ
A pull-up current. It can be
driven from a TTL or CMOS logic line or shorted
to ground with a switch
Voltage input.
Ground reference for all signals
Power-Fail Input - When this voltage monitor input
is less than 1.25V, PFO goes LOW. Connect PFI
to ground or V
CC
when not in use.
Power-Fail Output - This output is HIGH until PFI
is less than 1.25V.
Watchdog Input - If this input remains HIGH or
LOW for 1.6s, the internal watchdog timer times
out and WDO goes LOW. Floating WDI or
connecting WDI to a high-impedance tri-state
buffer disables the watchdog feature. The internal
watchdog timer clears whenever RESET is
asserted, WDI is tri-stated, or whenever WDI sees
a rising or falling edge.
No Connect.
Active-LOW RESET Output - This output pulses
LOW for 200ms when triggered and stays LOW
whenever V
CC
is below the reset threshold. It
remains LOW for 200ms after V
cc
rises above the
reset threshold or MR goes from LOW to HIGH.
A watchdog timeout will not trigger RESET unless
WDO is connected to MR.
Watchdog Output - This output pulls LOW when
the internal watchdog timer finishes its 1.6s count
and does not go HIGH again until the watchdog is
cleared. WDO also goes LOW during low-line
conditions. Whenever V
CC
is below the reset
threshold, WDO stays LOW. However, unlike
RESET, WDO does not have a minimum pulse
width. As soon as V
CC
is above the reset
threshold, WDO goes HIGH with no delay.
Active-HIGH RESET Output - This output is the
complement of RESET. Whenever RESET is
HIGH, RESET is LOW, and vice versa. Note the
SP708R/S/T
has a reset output only.
1
3
1
3
1
3
V
CC
GND
PFI
2
3
4
4
5
6
2
3
4
4
5
6
2
3
4
4
5
6
PFO
5
7
5
7
5
7
WDI
6
8
6
8
-
-
N.C.
-
-
-
-
6
8
RESET
-
-
7
1
7
1
WDO
8
2
8
2
-
-
RESET
7
1
-
-
8
2
Table 1. Device Pin Description
Date: 6-28-04
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
© Copyright 2004 Sipex Corporation
5
京公网安备 11010802033920号
EEWORLD
