Features
•
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
•
RapidS
™
Serial Interface: 66MHz Maximum Clock Frequency
•
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 512-Bytes per Page
– 528-Bytes per Page
– Page Size Can Be Factory Pre-configured for 512-Bytes
Page Program Operation
– Intelligent Programming Operation
– 4,096 Pages (512-/528-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (512-Bytes)
– Block Erase (4-Kbytes)
– Sector Erase (128-Kbytes)
– Chip Erase (16-Mbits)
Two SRAM Data Buffers (512-/528-Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25μA Standby Current Typical
– 15μA Deep Power Down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
•
•
16-megabit
2.5V or 2.7V
DataFlash
AT45DB161D
(Not Recommended
for New Designs)
•
•
•
•
•
•
•
•
•
•
•
1.
Description
The AT45DB161D is a 2.5V or 2.7V, serial-interface sequential access Flash memory
ideally suited for a wide variety of digital voice-, image-, program code- and data-stor-
age applications. The AT45DB161D supports RapidS serial interface for applications
requiring very high speed operations. RapidS serial interface is SPI compatible for
frequencies up to 66MHz. Its 17,301,504-bits of memory are organized as 4,096
pages of 512-bytes or 528-bytes each. In addition to the main memory, the
AT45DB161D also contains two SRAM buffers of 512-/528-bytes each. The buffers
allow the receiving of data while a page in the main Memory is being reprogrammed,
as well as writing a continuous data stream. EEPROM emulation (bit or byte alterabil-
ity) is easily handled with a self-contained three step read-modify-write
3500P–DFLASH–5/2013
operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a
parallel interface, the Adesto DataFlash
®
uses a RapidS serial interface to sequentially access its data. The simple
sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability,
minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and
industrial applications where high-density, low-pin count, low-voltage and low-power are essential.
To allow for simple in-system reprogrammability, the AT45DB161D does not require high input voltages for
programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program
and read operations. The AT45DB161D is enabled through the chip select pin (CS) and accessed via a three-wire
interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
2.
Pin Configurations and Pinouts
TSOP Top View: Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Figure 2-1.
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
Figure 2-2.
BGA Package Ball-out
(Top View)
1
2
3
4
5
A
B
C
NC
NC
NC
NC
NC
NC
SCK
GND
VCC
NC
CS
RDY/BSY
WP
NC
D
NC
SO
SI
RESET
NC
E
NC
NC
NC
NC
NC
Figure 2-3.
MLF (VDFN) Top View
SI
SCK
RESET
CS
1
2
3
4
Figure 2-4.
SO
7
GND
6
VCC
5
WP
8
SOIC Top View
SI
SCK
RESET
CS
1
2
3
4
8
7
6
5
SO
GND
VCC
WP
Note:
1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND
2
AT45DB161D
3500P–DFLASH–5/2013
AT45DB161D
Table 2-1.
Symbol
Pin Configurations
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not Deep Power-Down
mode), and the output pin (SO) will be in a high-impedance state. When the device is
deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation such
as a program or erase cycle, the device will not enter the standby mode until the completion of
the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched on the rising
edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector
Protection Register will be protected against program and erase operations regardless of
whether the Enable Sector Protection command has been issued or not. The WP pin functions
independently of the software controlled protection method. After the WP pin goes low, the
content of the Sector Protection Register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device
will simply ignore the command and perform no operation. The device will return to the idle state
once the CS pin has been deasserted. The Enable Sector Protection command and Sector
Lockdown command, however, will be recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to V
CC
whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset
the internal state machine to an idle state. The device will remain in the reset condition as long
as a low level is present on the RESET pin. Normal operation can resume once the RESET pin
is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended
that the RESET pin be driven high externally.
Ready/Busy: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through an external
pull-up resistor), will be pulled low during programming/erase operations, compare operations,
and page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Device Power Supply: The V
CC
pin is used to supply the source voltage to the device.
Operations at invalid V
CC
voltages may produce spurious results and should not be attempted.
Ground: The ground reference for the power supply. GND should be connected to the system
ground.
Asserte
d State
Type
CS
Low
Input
SCK
–
Input
SI
–
Input
Outpu
t
SO
–
WP
Low
Input
RESET
Low
Input
RDY/BUSY
–
Outpu
t
V
CC
GND
–
–
Power
Groun
d
3
3500P–DFLASH–5/2013
3.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (512-/528-BYTES)
BUFFER 1 (512-/528-BYTES)
BUFFER 2 (512-/528-BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
4.
Memory Array
To provide optimal flexibility, the memory array of the AT45DB161D is divided into three levels of granularity
comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each
level and details the number of pages per sector and block. All program operations to the DataFlash occur on a
page by page basis. The erase operations can be performed at the chip, sector, block or page level.
Figure 4-1.
Memory Architecture Diagram
BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0
BLOCK 1
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
4,096-/4,224-bytes
PAGE ARCHITECTURE
8 Pages
BLOCK 0
PAGE 0
PAGE 1
SECTOR 0b = 248 Pages
126,976-/130,944-bytes
SECTOR 1
BLOCK 2
PAGE 6
PAGE 7
PAGE 8
BLOCK 30
SECTOR 1 = 256 Pages
131,072-/135,168-bytes
BLOCK 31
BLOCK 33
SECTOR 2 = 256 Pages
131,072-/135,168-bytes
SECTOR 2
BLOCK 1
BLOCK 32
PAGE 9
PAGE 14
PAGE 15
BLOCK 62
BLOCK 63
BLOCK 64
SECTOR 14 = 256 Pages
131,072-/135,168-bytes
BLOCK 65
PAGE 16
PAGE 17
PAGE 18
SECTOR 15 = 256 Pages
131,072-/135,168-bytes
BLOCK 510
BLOCK 511
PAGE 4,094
PAGE 4,095
Block = 4,096-/4,224-bytes
Page = 512-/528-bytes
4
AT45DB161D
3500P–DFLASH–5/2013
AT45DB161D
5.
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their
associated opcodes are contained in
Table 15-1 on page 27
through
Table 15-7 on page 30.
A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory
address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired
buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are
transferred with the most significant bit (MSB) first.
Buffer addressing for standard DataFlash page size (528-bytes) is referenced in the datasheet using the
terminology BFA9 - BFA0 to denote the 10 address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0, where PA11 - PA0 denotes
the 12 address bits required to designate a page address and BA9 - BA0 denotes the 10 address bits required to
designate a byte address within the page.
For “Power of 2” binary page size (512-bytes) the Buffer addressing is referenced in the datasheet using the
conventional terminology BFA8 - BFA0 to denote the nine address bits required to designate a byte address within
a buffer. Main memory addressing is referenced using the terminology A20 - A0, where A20 - A9 denotes the 12
address bits required to designate a page address and A8 - A0 denotes the nine address bits required to designate
a byte address within a page.
6.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM
data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-
level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode.
6.1
Continuous Array Read (Legacy Command: E8H): Up to 66MHz
By supplying an initial starting address for the main memory array, the Continuous Array Read command can be
utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continuous read operation
without the need of additional address sequences. To perform a continuous read from the standard DataFlash
page size (528-bytes), an opcode of E8H must be clocked into the device followed by three address bytes (which
comprise the 24-bit page and byte address sequence) and four don’t care bytes. The first 12 bits (PA11 - PA0) of
the 22-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9 -
BA0) of the 22-bit address sequence specify the starting byte address within the page. To perform a continuous
read from the binary page size (512-bytes), the opcode (E8H) must be clocked into the device followed by three
address bytes and four don’t care bytes. The first 12 bits (A20 - A9) of the 21-bits sequence specify which page of
the main memory array to read, and the last nine bits (A8 - A0) of the 21-bits address sequence specify the starting
byte address within the page. The don’t care bytes that follow the address bytes are needed to initialize the read
operation. Following the don’t care bytes, additional clock pulses on the SCK pin will result in data being output on
the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the
reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device
will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover
(the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory
array has been read, the device will continue reading back at the beginning of the first page of memory. As with
crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
5
3500P–DFLASH–5/2013
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