Digital Video Encorders
Video bus interface
BU9969KN
No.09067EAT02
●Description
BU9969KN is a digital video encoder IC for NTSC/PAL (ITU-R BT.601,ITU-R BT.656).
It allows captured images (e.g. downloaded or on mobile phones) to be viewed on a TV monitor. In addition, a digital filter is
built in for high image quality, and both multifunction and simple types are available for greater compatibility.
●Features
・ Video Format
・ NTSC-M
・
PAL-B/D/G/H/I
・ Bus Interface
・ 656 input mode
・ 601 input mode
YCbCr 8 bit
( included in EAV, SAV )
( with Hsync, Vsync input )
(656 mode or 601 mode)
(601 mode)
YCbCr 16 bit or RGB 16 bit
4:2:2
R: 5bit, G: 6bit, B: 5bit
・ Input Data Format
・ YCbCr
・ RGB
・ Input Range
・ YCbCr:
1) Y: 16-235, CbCr: 16-240
2) YCbCr : 1-254
・ RGB: R, B: 0 - 31, G: 0 - 63
SCALE_M
*
= “1”
SCALE_M
*
= “0” (601 mode)
*SCALE_M is 1
st
bit of Sub-Address x’04.
・
・
・
・
・
・
・
・
NTSC/PAL Standard Video Output Support
Trap Filter Built In
x4 System Clock Over Sampling Function Built In
10-bit Video DAC Built In
PLL Built In
2-Wire Serial Interface
2 Supply Voltage Operation: (DVDD = PVDD = 1.8V : Typ, IOVDD = AVDD = 3.0V : Typ)
Package: VQFN36
●
Application
Cell Phone
www.rohm.com
©
2009 ROHM Co., Ltd. All rights reserved.
1/13
2009.05 - Rev.A
BU9969KN
Technical Note
●
Absolute Maximum Ratings
Table.1 Absolute Maximum Ratings
Item
[1.8V Power Source System]
Digital Core Power Source Voltage
PLL Power Source Voltage
[3.0V Power Source System]
Digital I/O power source voltage
DAC Power Source Voltage
Power Dissipation1
Power Dissipation2
Storage temperature range
IOVDD
AVDD
Pd1
Pd2
Tstg
450 (Note.1)
700 (Note.2)
-25 to 125
mW
mW
℃
-0.2 to 4.5
V
DVDD
PVDD
-0.2 to 2.5
V
Symbol
Rating
Unit
Note 1 : When not mounted on any board at Ta = 25℃.
Note 2 : When mounted on 50mm*58mm*1.6mm glass epoxy board. In the case to use at Ta = 25C or
higher, 11.3 mW should be decreased per 1C. This value is an actually measured value, and
not a guaranteed value.
●
Recommended Operation Range
Table.2 Recommended Operation Range
Item
[1.8V Power Source System]
Digital Core Power Source Voltage
PLL Power Source Voltage
[3.0V Power Source System]
Digital I/O power source voltage*
DAC Power Source Voltage
Operation temperature range
IOVDD
AVDD
Topr
-20 to 70
℃
3.00 ± 0.3
V
DVDD
PVDD
1.80 ± 0.1
V
Symbol
Range
Unit
*Connect the pull-up resistance of the serial interface to the digital I/O power source voltage.
*Supply the power source voltage to all power source pins within 100 μsec.
This procedure is same, when stopping to supply the power source.
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©
2009 ROHM Co., Ltd. All rights reserved.
2/13
2009.05 - Rev.A
BU9969KN
Technical Note
●
Recommended Operating Conditions
Table.3 Recommended Operating Conditions
(Unless otherwise specified Ta=25C, DVDD=PVDD=1.8V, IOVDD=AVDD=3.0V, GND=0V)
Item
<Image data interface>
SYSCLK frequency 1
SYSCLK frequency 2
SYSCLK frequency deviation 1
SYSCLK frequency deviation 2
SYSCLK rise time
SYSCLK fall time
SYSCLK duty
<Serial interface>
SCLK frequency
SCLK rise time
SCLK fall time
SDI rise time
SDI fall time
SCLK ”L” pulse width
SCLK ”H” pulse width
*1
Symbol
fsysclk1
fsysclk2
dfsysclk1
dfsysclk2
t2r
t2f
dutysclk
f
SCLK
t1sr
t1sf
t1dr
t1df
t1wl
t1wh
Min
-
-
Typ
27
13.5
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
Unit
MHz
MHz
ppm
ppm
ns
ns
%
kHz
ns
ns
ns
ns
½s
½s
Condition
656 input mode
601 input mode
27MHz at 656 input mode
13.5MHz at 601 input mode
*1
*1
*1
-100
-100
-
-
45
-
-
-
-
-
1.3
0.6
100
100
5
5
55
400
300
300
300
300
-
-
*1
*1
*1
*1
*1
*1
Refer to Fig.5 the serial interface-timing chart on page 9.
●
Electric Characteristics 1
Table 4.1 Electric Characteristics 1
(Unless otherwise specified Ta=25C, DVDD=PVDD=1.8V, IOVDD=AVDD=3.0V, GND=0V)
Item
<Image data interface>
Data setup time
Data hold time
HS, VS setup time
HS, VS hold time
<Serial interface>
Data hold time
Data setup time
Hold time (START)
Setup time (STOP)
Setup time (START)
Bus free time
Between "STOP" condition
and "START" condition
*1
*2
Symbol
t2sd
t2hd
t2sc
t2hc
½1½
t1s
t1hSTA
t1sSTO
t1sSTA
tBUF
Min
5
8
5
8
0
100
0.6
0.6
0.6
1.3
Typ
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.9
-
-
-
-
-
Unit
ns
ns
ns
ns
½s
ns
½s
½s
½s
½s
Condition
*1
*1
*1
*1
*2
*2
*2
*2
*2
*2
Refer to Fig.3., the image data and synchronous signal-timing chart on page 8.
Refer to Fig.5., the serial interface timing chart on page 9.
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©
2009 ROHM Co., Ltd. All rights reserved.
3/13
2009.05 - Rev.A
BU9969KN
Technical Note
●
Electric Characteristics 2
Table 4.2 Electric Characteristics 2
(Unless otherwise specified Ta=25C, DVDD=PVDD=1.8V, IOVDD=AVDD=3.0V, GND=0V)
Item
Symbol
Min
-
-
-
-
IOVDD
*0.8
-0.2
Typ
20
0.5
1.5
0.5
-
-
Max
50
10.0
8
2
IOVDD
+0.2
IOVDD
*0.2
Unit
mA
mA
½A
½A
V
V
½A
½A
½A
V
*1
*2
*3
*4
*4
*5
Condition
<Video encoder digital portion>
Digital core dynamic current
IDDCO
Digital I/O dynamic current
IDDIO
Digital core static current
ISTDCO
Digital I/O static current
ISTDIO
"H" input voltage
V
IH
"L" input voltage
L input leak current 1
L input leak current 2
H input leak current 1
H input leak current 2
SDI "L" output voltage
*1
*2
*3
*4
*5
*6
*7
*8
V
IL
I
ILL1
I
ILL2
I
IHL
I
IHT
V
OL
-10
-10
10
0
-
-
-
-
10
10
500
0.5
*6
*7
*8 IOL=2mA
Internal Color Bar output mode at 27MHz operation.
RESETB = Low
RESETB = Low and All inputs pins = Low
The following pins are applied.
SYSCLK, DATA[15:0], HS, VS, TEST[3:0], SCLK and SDI.
The following pins are set to “Low”.
SYSCLK, DATA[15:0], HS, VS, TEST[3:0], SCLK and SDI.
The following pins are set to “High (IOVDD)”.
SYSCLK, DATA[15:0], HS, VS, SCLK and SDI.
The following pins are set to “High (IOVDD)”.
TEST [3:0]
The SDI pin is applied.
●
Electric Characteristics 3
Table 4.3 Electric Characteristics 3
(Unless otherwise specified Ta=25C, DVDD=PVDD=1.8V, IOVDD=AVDD=3.0V, GND=0V)
Item
<Video DAC portion>
Video DAC resolution
Video DAC dynamic current
Video DAC static current
Integral linearity error
Differential linearity error
Full scale voltage
<PLL portion>
PLL dynamic current
PLL static current
*1
*2
Symbol
RES
IDDV
ISTV
INL
DNL
V
FS
IDDP
ISTP
Min
-
-
-
-
-
1.1
-
-
Typ
-
40
1
±8.0
±1.0
1.25
1
1
Max
10
55
5
±15.0
±4.0
1.4
2.5
5
Unit
bit
mA
½A
LSB
LSB
V
mA
uA
Condition
R
L
=37.5Ω,R
IREF
=1.2kΩ *1
RESETB=L *2
R
L
=37.5Ω,R
IREF
=1.2kΩ *1
R
L
=37.5Ω,R
IREF
=1.2kΩ *1
R
L
=37.5Ω,R
IREF
=1.2kΩ *1
SYSCLK=27MHz input
*2
R
L
=37.5Ω shows the value at measurement.
Set the RESETB or 1
st
bit of register PWD_M to “Low”.
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©
2009 ROHM Co., Ltd. All rights reserved.
4/13
2009.05 - Rev.A
BU9969KN
Technical Note
●
Block Diagram
Y
RESETB
Host I/F
DATA[15:0]
HS
VS
SYSCLK
Cr
Timing
Generator
Cb
over
sampling
Gamma
Correction
Y
LPF
TRAP
Color Bar
Generator
over
sampling
LPF
over
sampling
10bit
DAC
VOUT
over
sampling
LPF
VREF
Generator
Sub Carrier
Generator
Serial Interface
IREF
PLL
13.5/27MHz
54MHz
SCLK
SDI
Fig.1. BU9969KN Block Diagram
●
Terminal Functions
36
35
34
33
32
31
30
29
TEST1
PVDD
RESETB
SDI
TEST3
TEST2
1
2
3
4
5
6
7
8
9
DATA [0]
PLL
DATA [1]
DATA [2]
DATA [3]
DATA [4]
DATA [5]
DATA [6]
DATA [7]
DATA [8]
DATA [10]
DATA [11]
DATA [12]
DATA [13]
DATA [14]
DATA [15]
DATA [9]
SYSCLK
DVDD
MAIN LOGIC
DAC
TEST0
VOUT
AVDD
IREF
GND
N.C.
IOVDD
GND
VS
HS
GND
SCLK
28
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
Fig 2. BU9969KN Terminal Layout
www.rohm.com
©
2009 ROHM Co., Ltd. All rights reserved.
5/13
18
2009.05 - Rev.A
Talking
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