and/or fractional divides are allowed on two of the PLLs.
There are a total of six 8-bit output dividers.The outputs are
connected to the PLLs via a switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function is programmable.
IDT5V19EE904
Features
•
•
•
•
•
•
Four internal PLLs
Internal non-volatile EEPROM
Fast (400kHz) mode I
2
C serial interface
Input frequency range: 1 MHz to 200 MHz
Output frequency range: 4.9 kHz to 200 MHz
Reference crystal input with programmable linear load
capacitance
– Crystal frequency range: 8 MHz to 50 MHz
(maximum crystal range is best effort)
•
Integrated VCXO
•
Four independently controlled VDDO (1.8V - 3.3V)
•
Each PLL has a 7-bit reference divider and a 12-bit
feedback-divider
•
8-bit output-divider blocks
•
Fractional division capability on one PLL
•
Two of the PLLs support spread spectrum generation
capability
•
I/O Standards:
– Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS
– Inputs - 3.3 V LVTTL/ LVCMOS
•
•
•
•
•
•
•
•
•
Programmable slew rate control
Programmable loop bandwidth
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with auto and manual switchover
options
Individual output enable/disable
Power-down mode
3.3V core V
DD
Available in VFQFPN package
-40 to +85 C Industrial Temp operation
IDT®
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
1
IDT5V19EE904
REV N 092412
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
Functional Block Diagram
S
R
C
0
S
R
C
1
S
R
C
2
S
R
C
4
S
R
C
3
S
R
C
6
Control
Logic
S
R
C
5
S1
OUT0
XIN/REF
XOUT
PLL0 (SS)
VCXO
/DIV1
OUT1
VIN
controlled
Logic
CLKIN
PLL1
/DIV2
OUT2
CLKSEL
PLL2
OUT4
/DIV4
OUT4
S3
PLL3 (SS)
/DIV3
OUT3
SD/OE
SDA
SCL
SEL[2:0]
/DIV6
OUT6
OUT5
/DIV5
OUT5
1. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors.
IDT®
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
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IDT5V19EE904
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EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Configuration
VDDO3
SD/OE
OUT0
SEL1
SEL2
SEL0
GND
31
VDD
32
29
28
27
26
25
30
VIN
XOUT
XIN/REF
VDD
CLKIN
GND
OUT1
OUT2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OUT3
OUT6
GND
VDD
CLKSEL
SCLK
SDAT
GND
12
10
OUT4
11
13
14
15
16
Pin Descriptions
Pin Name
VIN
CLKIN
XOUT
XIN / REF
SDAT
9
VDDO1
OUT5b
OUT5
32 pin VFQFPN
(Top View)
OUT4b
NL32
Pin#
1
5
2
3
18
VDDO4
GND
VDDO5
I/O
I
I
O
I
I/O
Pin Type
LVTTL
LVTTL
LVTTL
LVTTL
Open Drain
Pin Description
VCXO analog control voltage input. Pulls output
±
100ppm by varying from 0V to 3.3V.
Input clock. Weak internal pull down resistor.
CRYSTAL_OUT -- Reference crystal feedback.
CRYSTAL_IN -- Reference crystal input or external
reference clock input.
Bidirectional I
2
C data. An external pull-up resistor is
required. See I
2
C specification for pull-up value
recommendation.
I
2
C clock. An external pull-up resistor is required. See
I
2
C specification for pull-up value recommendation.
Input clock selector. Weak internal pull down resistor.
Configuration select pin. Weak internal pull down
resistor.
Configuration select pin. Weak internal pull down
resistor.
Configuration select pin. Weak internal pull down
resistor.
Enables/disables the outputs or powers down the chip.
The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW. (Default is active LOW.)
Weak internal pull down resistor.
SCLK
CLKSEL
SEL2
SEL1
SEL0
SD/OE
19
20
26
27
28
29
I
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
IDT®
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
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EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
Pin Name
OUT0
OUT1
OUT2
OUT3
OUT4
OUT4b
OUT5
OUT5b
OUT6
NL32
Pin#
30
7
8
24
10
11
14
15
23
32
4
21
9
25
12
16
6, 13,
17, 22,
31,PAD
I/O
O
O
O
O
O
O
O
O
O
Pin Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
1
LVTTL
Power
Power
Power
Power
Power
Power
Power
Power
Pin Description
Configurable clock output 0. 3.3V LVTTL levels.
Configurable clock output 1. Output levels controlled by
VDDO1.
Configurable clock output 2. Output levels controlled by
VDDO1.
Configurable clock output 3. Output levels controlled by
VDDO3.
Configurable clock output 4. Output levels controlled by
VDDO4.
Configurable clock output 4b. Output levels controlled by
VDDO4.
Configurable clock output 5. Output levels controlled by
VDDO5.
Configurable clock output 5b. Output levels controlled by
VDDO5.
Configurable clock output 6. Output levels controlled by
VDDO3.
Device power supply. Connect to 3.3V.
Crystal oscillator power supply. Connect to 3.3V through
5Ω resistor. Use filtered analog power supply if available.
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT1 and OUT2.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT3 and OUT6.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT4 and OUT4b.
Device power supply. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT5 and OUT5b.
Connect to Ground.
VDD
VDDx
AVDD
VDDO1
VDDO3
VDDO4
VDDO5
GND
1. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
2. Analog power plane should be isolated from a 3.3V power plane through a ferrite bead.
3. Each power pin should have a dedicated 0.01µF de-coupling capacitor. Digital VDDs may be tied together.
4. Unused clock inputs (REFIN or CLKIN) must be pulled high or low - they cannot be left floating. If the crystal oscillator is not used, XOUT must be left floating.
IDT®
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
4
IDT5V19EE904
REV N 092412
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
PLL Features and Descriptions
7-bit
D
VCO
4-bit
A
12-bit
N
Sigm a-Delta
M odulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
(D)
1
Values
PLL0
PLL1
PLL2
PLL3
1 - 127
1 - 127
1 - 127
3 - 127
Multiplier
(M)
2
Values
10 - 8206
1 - 4095
1 - 4095
12 - 4095
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
Yes
Yes
Yes
Yes
Yes
No
No
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
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