Data Sheet
FEATURES
2.5 GSPS internal clock speed
Integrated 12-bit DAC
Frequency tuning resolution to 135 pHz
16-bit phase tuning resolution
12-bit amplitude scaling
Programmable modulus
Automatic linear and nonlinear frequency sweeping
capability
32-bit parallel datapath interface
8 frequency/phase offset profiles
Phase noise: −128 dBc/Hz (1 kHz offset at 978 MHz)
Wideband SFDR < −57 dBc
Serial or parallel I/O control
1.8 V/3.3 V power supplies
2.5 GSPS Direct Digital Synthesizer
with 12-Bit DAC
AD9915
Software and hardware controlled power-down
88-lead LFCSP package
PLL REF CLK multiplier
Phase modulation capability
Amplitude modulation capability
Multichip synchronization
APPLICATIONS
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
Polar modulator
Fast frequency hopping
FUNCTIONAL BLOCK DIAGRAM
AD9915
HIGH SPEED PARALLEL
MODULATION
PORT
LINEAR
SWEEP
BLOCK
2.5GSPS DDS CORE
12-BIT DAC
REF CLK
MULTIPLIER
TIMING AND CONTROL
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
10837-001
SERIAL OR PARALLEL
DATA PORT
AD9915
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Performance .................................................................. 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Single Tone Mode ....................................................................... 17
Profile Modulation Mode .......................................................... 17
Digital Ramp Modulation Mode .............................................. 17
Parallel Data Port Modulation Mode....................................... 17
Programmable Modulus Mode................................................. 17
Mode Priority .............................................................................. 18
Functional Block Detail ................................................................. 19
DDS Core..................................................................................... 19
Data Sheet
12-Bit DAC Output .................................................................... 20
DAC Calibration Output ........................................................... 20
Reconstruction Filter ................................................................. 20
Clock Input (REF_CLK/REF_CLK) ........................................ 21
PLL Lock Indication .................................................................. 22
Output Shift Keying (OSK) ....................................................... 22
Digital Ramp Generator (DRG) ............................................... 23
Power-Down Control ................................................................ 27
Programming and Function pins ................................................. 28
Serial Programming ....................................................................... 31
Control Interface—Serial I/O ................................................... 31
General Serial I/O Operation ................................................... 31
Instruction Byte .......................................................................... 31
Serial I/O Port Pin Descriptions .............................................. 31
Serial I/O Timing Diagrams ..................................................... 32
MSB/LSB Transfers .................................................................... 32
Parallel Programming (8-/16-Bit) ................................................ 33
Multiple Chip Synchronization .................................................... 34
Register Map and Bit Descriptions .............................................. 36
Register Bit Descriptions ........................................................... 41
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
REVISION HISTORY
8/12—Rev. 0 to Rev. A
Changed External Clock Frequency from 3.5 GHz to 2.5 GHz
and Differential Input Voltage Unit from mV p-p to V p-p ....... 4
Updated Outline Dimensions ....................................................... 47
7/12—Revision 0: Initial Version
Rev. A | Page 2 of 48
Data Sheet
GENERAL DESCRIPTION
The
AD9915
is a direct digital synthesizer (DDS) featuring a
12-bit DAC. The
AD9915
uses advanced DDS technology,
coupled with an internal high speed, high performance DAC
to form a digitally programmable, complete high frequency
synthesizer capable of generating a frequency-agile analog
output sinusoidal waveform at up to 1.0 GHz. The
AD9915
enables fast frequency hopping and fine tuning resolution
(64-bit capable using programmable modulus mode). The
AD9915
also offers fast phase and amplitude hopping capability.
The frequency tuning and control words are loaded into the
AD9915
via a serial or parallel I/O port. The
AD9915
also
AD9915
supports a user defined linear sweep mode of operation for
generating linear swept waveforms of frequency, phase, or
amplitude. A high speed, 32-bit parallel data input port is
included, enabling high data rates for polar modulation
schemes and fast reprogramming of the phase, frequency, and
amplitude tuning words.
The
AD9915
is specified to operate over the extended industrial
temperature range (see the Absolute Maximum Ratings
section).
AD9915
OSK
DRCTL
DRHOLD
DROVER
2
OUTPUT
SHIFT
KEYING
DIGITAL
RAMP
GENERATOR
DDS
AMPLITUDE (A)
PHASE (θ)
A
DAC_RSET
Acos (ωt + θ)
DAC
12-BIT
AOUT
AOUT
3
PS[2:0]
I/O_UPDATE
32
D0 TO D31
INTERNAL
PROGRAMMING
REGISTERS
DATA
θ
ROUTE
FREQUENCY (ω)
Asin (ωt + θ)
AND
ω
PARTITION
CONTROL
CLOCK
SYSCLK
INTERNAL CLOCK TIMING
AND CONTROL
REF_CLK
REF_CLK
PLL
4
F0 TO F3
SYNC_CLK
POWER-
DOWN
CONTROL
MULTICHIP
SYNCHRONIZATION
EXT_PWR_DWN
LOOP_FILTER
SYNC_IN
MASTER_RESET
SYNC_OUT
Figure 2. Detailed Block Diagram
Rev.
A
| Page 3 of 48
10837-002
AD9915
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, T
A
= 25°C, R
SET
= 3.3 kΩ,
I
OUT
= 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
DVDD_I/O
DVDD
AVDD (3.3V)
AVDD (1.8V)
SUPPLY CURRENT
I
DVDD_I/O
I
DVDD
I
AVDD(3.3V)
I
AVDD(1.8V)
TOTAL POWER DISSIPATION
Base DDS Power, PLL Disabled
Base DDS Power, PLL Enabled
Linear Sweep Additional Power
Modulus Additional Power
Amplitude Scaler Additional
Power
Full Power-Down Mode
CMOS LOGIC INPUTS
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Input Current (I
INH
, I
INL
)
Maximum Input Capacitance (C
IN
)
CMOS LOGIC OUTPUTS
Output High Voltage (V
OH
)
Output High Voltage (V
OL
)
REF CLK INPUT CHARACTERISTICS
REF CLK Multiplier Bypassed
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
REF CLK Multiplier Enabled
Input Capacitance
Input Resistance
Internally Generated DC Bias
Voltage
Differential Input Voltage
3.135
1.71
3.135
1.71
3.30
1.80
3.30
1.80
3.465
1.89
3.465
1.89
20
270
640
148
V
V
V
V
mA
mA
mA
mA
mW
mW
mW
mW
mW
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
See also the total power dissipation specifications
Pin 16, Pin 83
Pin 6, Pin 23, Pin 73
Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52,
Pin 53, Pin 60
Pin 32, Pin 56, Pin 57
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2.5 GHz, single-tone mode, modules disabled, linear
sweep disabled, amplitude scaler disabled
2138
2237
28
20
138
400
2797
2890
Manual or automatic
Using either the power-down and enable register or the
EXT_PWR_DWN pin
616
mW
2.0
±60
3
2.7
DVDD_I/O
0.8
±200
V
V
μA
pF
V
V
At V
IN
= 0 V and V
IN
= DVDD_I/O
DVDD_I/O
0.4
I
OH
= 1 mA
I
OL
= 1 mA
REF CLK inputs should always be ac-coupled (both single-
ended and differential)
Single-ended, each pin
Differential
1
1.4
2
0.8
1
1.4
2
0.8
1.5
1.5
pF
kΩ
V
V p-p
pF
kΩ
V
V p-p
Single-ended, each pin
Differential
Rev. A | Page 4 of 48
Data Sheet
AC SPECIFICATIONS
AD9915
AVDD (1.8V) and DVDD (1.8V) = 1.8 V ± 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V ± 5%, T
A
= 25°C, R
SET
= 3.3 kΩ, I
OUT
=
20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted.
Table 2.
Parameter
REF CLK INPUT
REF CLK Multiplier Bypassed
Input Frequency Range
Duty Cycle
Minimum Differential Input Level
System Clock (SYSCLK) PLL Enabled
VCO Frequency Range
VCO Gain (K
V
)
Maximum PFD Rate
CLOCK DRIVERS
SYNC_CLK Output Driver
Frequency Range
Duty Cycle
Rise Time/Fall Time (20% to 80%)
SYNC_OUT Output Driver
Frequency Range
Duty Cycle
Rise Time (20% to 80%)
Fall Time (20% to 80%)
DAC OUTPUT CHARACTERISTICS
Output Frequency Range (1
st
Nyquist
Zone)
Output Resistance
Output Capacitance
Full-Scale Output Current
Gain Error
Output Offset
Voltage Compliance Range
Wideband SFDR
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
978.2 MHz Output
Narrow-Band SFDR
122.5 MHz Output
305.3 MHz Output
497.5 MHz Output
978.2 MHz Output
DIGITAL TIMING SPECIFICATIONS
Time Required to Enter Power-Down
Time Required to Leave Power-Down
Minimum Master Reset time
Maximum DAC Calibration Time (t
CAL
)
Maximum PLL Calibration Time (t
REF_CLK
)
Maximum Profile Toggle Rate
−67
−66
−59
−60
dBc
dBc
dBc
dBc
Min
Typ
Max
Unit
Test Conditions/Comments
Input frequency range
Maximum f
OUT
is 0.4 × f
SYSCLK
Equivalent to 316 mV swing on each leg
500
45
632
2400
60
2500
55
MHz
%
mV p-p
MHz
MHz/V
MHz
2500
125
45
50
650
156
55
MHz
%
ps
10 pF load
MHz
%
ps
ps
MHz
Ω
pF
mA
% FS
μA
V
Single-ended (each pin internally terminated to
AVDD (3.3V))
Range depends on DAC R
SET
resistor
33
1350
1670
0
50
5
−10
AVDD −
0.50
6.5
66
CFR2 register, Bit 9 = 1
10 pF load
10 pF load
1250
20.48
+10
0.6
AVDD +
0.50
−95
−95
−95
−92
45
250
24
152
16
8
1
dBc
dBc
dBc
dBc
ns
ns
SYSCLK cycles
µs
ms
ms
SYNC_CLK period
See the Typical Performance Characteristics
section
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
0 MHz to 1250 MHz
See the Typical Performance Characteristics
section
±500 kHz
±500 kHz
±500 kHz
±500 kHz
Power-down mode loses DAC/PLL calibration
settings
Must recalibrate DAC/PLL
f
CAL
= f
SYSCLK
/384 USR0 register, Bit 6 = 0; see the
DAC Calibration Output section for formula
PFD rate = 25 MHz
PFD rate = 50 MHz
Rev.
A
| Page 5 of 48
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