Changes to Ordering Guide .......................................................... 25
10/04—Rev. A to Rev. B
Updated Format ................................................................. Universal
Changes to Specifications .................................................................3
Changes to One-Time Programming (OTP) Section................ 13
Changes to Power Supply Considerations Section .................... 15
Changes to Figure 44 and Figure 45............................................. 15
Changes to Figure 46 and Figure 47............................................. 16
11/03—Rev. 0 to Rev. A
Changes to Electrical Characteristics—2.5 kΩ..............................3
11/03—Revision 0: Initial Version
Rev. H | Page 2 of 24
AD5172/AD5173
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE
4
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
6
Capacitance A, B
7
Capacitance W
7
Shutdown Supply Current
8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High
9
Input Logic Low
9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance
7
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage
9, 10
Supply Current
OTP Supply Current
9, 11, 12
Power Dissipation
13
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
14
Bandwidth, −3 dB
Total Harmonic Distortion
Symbol
R-DNL
R-INL
∆R
AB
(∆R
AB
/R
AB
)/∆T
R
WB
Conditions
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
Code = 0x00, V
DD
= 5 V
Min
−2
−14
−20
Typ
1
±0.1
±2
35
160
Max
+2
+14
+55
200
Unit
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(ΔV
W
/V
W
)/ΔT
V
WFSE
V
WZSE
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
A_SD
I
CM
−1.5
−2
Code = 0x80
Code = 0xFF
Code = 0x00
−14
0
GND
f = 1 MHz, measured to
GND, code = 0x80
f = 1 MHz, measured to
GND, code = 0x80
V
DD
= 5.5 V
V
A
= V
B
= V
DD
/2
±0.1
±0.6
15
−5.5
4.5
+1.5
+2
0
12
V
DD
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
45
60
0.01
1
1
μA
nA
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD_RANGE
V
DD_OTP
I
DD
I
DD_OTP
P
DISS
PSS
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
0.7 V
DD
−0.5
2.1
V
DD
+ 0.5
+0.3 V
DD
V
V
V
V
μA
pF
V
V
μA
mA
μW
%/%
0.6
±1
5
2.7
5.6
5.5
5.8
6
33
±0.08
T
A
= 25°C
V
IH
= 5 V or V
IL
= 0 V
V
DD_OTP
= 5.0 V, T
A
= 25°C
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
V
DD
= 5 V ± 10%,
code = midscale
Code = 0x80
V
A
= 1 V rms, V
B
= 0 V,
f = 1 kHz
5.7
3.5
100
±0.02
BW
THD
W
4.8
0.1
MHz
%
Rev. H | Page 3 of 24
AD5172/AD5173
Parameter
V
W
Settling Time
Resistor Noise Voltage Density
1
2
Symbol
t
S
e
N_WB
Conditions
V
A
= 5 V, V
B
= 0 V, ±1 LSB
error band
R
WB
= 1.25 kΩ, R
S
= 0 Ω
Min
Typ
1
1
3.2
Max
Unit
μs
nV/√Hz
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
A
= V
DD
, V
B
= 0 V, wiper (V
W
) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the V
IH
is 0.7 V × V
DD
. For example, V
IH
minimum = 3.5 V when V
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V
DD
.
However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
14
All dynamic characteristics use V
DD
= 5 V.
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ
V
DD
= 5 V ± 10% or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE
4
Differential Nonlinearity
5
Integral Nonlinearity
5
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
6
Capacitance A, B
7
Capacitance W
7
Shutdown Supply Current
8
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
SDA and SCL
Input Logic High
9
Input Logic Low
9
AD0 and AD1
Input Logic High
Input Logic Low
Input Current
Input Capacitance
7
Symbol
R-DNL
R-INL
ΔR
AB
(ΔR
AB
/R
AB
)/ΔT
R
WB
Conditions
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
Code = 0x00, V
DD
= 5 V
Min
−1
−2.5
−20
Typ
1
±0.1
±0.25
35
160
Max
+1
+2.5
+20
200
Unit
LSB
LSB
%
ppm/°C
Ω
DNL
INL
(ΔV
W
/V
W
)/ΔT
V
WFSE
V
WZSE
V
A
, V
B
, V
W
C
A
, C
B
C
W
I
A_SD
I
CM
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−2.5
0
GND
f = 1 MHz, measured to
GND, code = 0x80
f = 1 MHz, measured to
GND, code = 0x80
V
DD
= 5.5 V
V
A
= V
B
= V
DD
/2
±0.1
±0.3
15
−1
1
+1
+1
0
2.5
V
DD
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
45
60
0.01
1
1
μA
nA
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
0.7 V
DD
−0.5
2.1
V
DD
+ 0.5
+0.3 V
DD
V
V
V
V
μA
pF
0.6
±1
5
Rev. H | Page 4 of 24
AD5172/AD5173
Parameter
POWER SUPPLIES
Power Supply Range
OTP Supply Voltage
9, 10
Supply Current
OTP Supply Current
9, 11, 12
Power Dissipation
13
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
14
Bandwidth, −3 dB
Symbol
V
DD_RANGE
V
DD_OTP
I
DD
I
DD_OTP
P
DISS
PSS
Conditions
Min
2.7
5.6
Typ
1
Max
5.5
5.8
6
33
±0.02
±0.08
Unit
V
V
μA
mA
μW
%/%
T
A
= 25°C
V
IH
= 5 V or V
IL
= 0 V
V
DD_OTP
= 5.0 V, T
A
= 25°C
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= 5 V
V
DD
= 5 V ± 10%,
code = midscale
R
AB
= 10 kΩ, code = 0x80
R
AB
= 50 kΩ, code = 0x80
R
AB
= 100 kΩ, code = 0x80
V
A
= 1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 kΩ
V
A
= 5 V, V
B
= 0 V, ±1 LSB
error band
R
WB
= 5 kΩ, R
S
= 0 Ω
5.7
3.5
100
BW
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
1
2
THD
W
t
S
e
N_WB
600
100
40
0.1
2
9
kHz
kHz
kHz
%
μs
nV/√Hz
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
A
= V
DD
, V
B
= 0 V, wiper (V
W
) = no connect.
4
Specifications apply to all VRs.
5
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
7
Guaranteed by design, but not subject to production test.
8
Measured at Terminal A. Terminal A is open circuited in shutdown mode.
9
The minimum voltage requirement on the V
IH
is 0.7 V × V
DD
. For example, V
IH
minimum = 3.5 V when V
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up to V
DD
.
However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.
10
Different from the operating power supply; the power supply for OTP is used one time only.
11
Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.
12
See Figure 30 for an energy plot during an OTP program.
13
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
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