Integrated Linear DDR
Termination Regulator
POWER MANAGEMENT
Description
The SC2595 is an integrated linear DDR termination
device, which provides a complete solution for DDR
termination designs; while meeting the JEDEC require-
ments of SSTL-2 specifications for DDR-SDRAM termi-
nation.
The SC2595 can source and sink 1.5A current at the
output V
TT
while maintaining excellent load regulation.
V
TT
is designed to track the V
REF
voltage with a tight
tolerance over the entire current range while preventing
shoot through on the output stage.
A V
SENSE
pin is incorporated to provide excellent load
regulation, along with a buffered reference voltage.
The SC2595 incorporates a disable function built into
the AV
CC
pin to tri-state the output during Suspend To
Ram (STR) states.
(Multiple patents pending.)
SC2595
Features
Regulates while sourcing or sinking 1.5A
AV
CC
range is from 2.5V to 5V
Reference output
Minimum number of external components
Accurate internal voltage divider
SOIC8-EDP package.Pb-free,Halogen free, and RoHS/
WEEE compliant
Applications
DDR memory termination
High speed data line termination
PC motherboards
Graphics boards
Disk drives
CD-ROM drives
Typical Application Circuit
VDD
SC2595
1
2
3
VREF
4
NC
GND
VSENSE
VREF
VTT
PVCC
AVCC
VDDQ
8
7
6
5
VTT
September 24, 2009
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SC2595
POWER MANAGEMENT
Absolute Maximum Ratings
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied.
P ar am et er
PVCC, AVCC, VDDQ to GN D
Thermal Resistance Junction to Case
SOIC8-EDP
Thermal Resistance Junction to Ambient
SOIC8-EDP
Op erating Temp erature Range
Op erating Junction Temp erature Range
Storage Temp erature Range
Peak IR Reflow Temp erature 10 - 40s
Peak IR Reflow Temp erature 10 - 40s
ESD Rating (Human Body Model)
S y m b ol
V
CC
θ
JC
θ
JA
T
A
T
J
T
STG
T
LE A D
T
LE A D
ESD
M ax i m u m
-0.3 to +6.0
5.5
Units
V
°C/W
36.5
-40 to +105
-40 to +150
-65 to +150
240
260
2
°C/W
°C
°C
°C
°C
°C
KV
Operating Range
P ar am et er
Junction Temp erature Range
AVCC to GN D
PVCC to GN D
S y m b ol
T
J
AV
CC
PV
CC
M ax i m u m
-40 to +150
2.3 to 5.5
2.3 to AV
CC
Units
°C
V
V
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25
o
C and limits in boldface type apply over the full Operating Temperature Range
(T
J
= -40
o
C to +150
o
C). Unless otherwise specified, AV
CC
= PV
CC
= 2.5V, V
DDQ
= 2.5V.
P ar am et er
Reference Voltage
Load Regulation
(1)
S y m b ol
V
REF
REG
LOAD
V OS
V TT
I
Q
Te s t C o n d i t i o n s
I
REF_OUT
= 0mA
I
LOAD
: 0 to +1.5A
I
LOAD
: 0 to -1.5A
I
OUT
=0A , V
TT
- V
REF
I
LOAD
= 0A
Min
V DDQ/2
- 40mV
Ty p
1.25
-0.5
+0.5
M ax
V DDQ/2
+ 40mV
Units
V
%
V TT Outp ut Voltage Offset
Quiescent Current
AV CC Enab le Threshold
V DDQ Inp ut Imp edance
-20
0
400
2.1
+20
mV
μ
A
V
kΩ
Z
VDDQ
100
Note:
(1) For Load Regulation, use a 10ms current pulse width when measuring V
TT
.
©2009
Semtech Corp.
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SC2595
POWER MANAGEMENT
Pin Descriptions
S O I C- 8L E DP
Pin #
1
2
3
P i n N am e
NC
GN D
V SEN SE
N o internal connection.
Ground.
V
SENSE
is a feedb ack p in. V
TT
p lane is always a narrow and long strip p lane in most
m o t h e r b o ar d ap p l i cat i o n s. T h i s l o n g st r i p p l an e w i l l cau se a l ar g e t r ace
inductance and trace resistance. Consider the load transient condition; a fast
load current going through V
TT
strip p lane can create voltage sp ikes on the V
TT
p lane. The load current can also cause a DC voltage drop on the V
TT
p lane. It is
recommen d ed th at V
SEN SE
sh ou l d b e con n ected to th e cen ter of V
TT
p l an e to
i mp rove th e l oad regu l ati on an d th e n oi se i mmu n i ty. In case th at on e can 't
connect the V
SENSE
p in to the center of the V
TT
p lane, one should connect it to the
SC2595 V
TT
p in directly. A longer trace of V
SENSE
may p ick up noise and cause the
error of load regulation; hence the longer trace must b e avoided.
A 10nF to 100nF ceramic cap acitor close to the V
SENSE
p in is req uired to avoid
oscillation during transient condition.
V
REF
is an outp ut p in, which p rovides the b uffered outp ut of the internal reference
voltage. System designer can use the V
REF
outp ut voltage for N or thb ridge chip set
an d memory. B ecau se th ese i n p u t p i n s are ty p i cal l y h i gh i mp ed an ce, th ere
should b e a small amount of current drawn from the V
REF
p in [figure 9, 10]. To
imp rove the noise immunity, a ceramic cap acitor (10nF - 100nF) should b e added
from the V
REF
p in to ground with shor t distance.
The V
DDQ
p in is an inp ut for creating internal reference voltage to regulate V
TT.
The
V
DDQ
voltage is connected to internal 100Kohm resistor divider. The central tap
of resi stor d i vi d er ( V
DDQ
/2) i s con n ected to th e i n tern al vol tage b u ffer, w h i ch
outp ut is connected to V
REF
p in and the non-inver ting inp ut of the error amp lifier
as the reference voltage. With the feedb ack loop closed, the V
TT
outp ut voltage
will always track the V
DDQ
/2 p recisely. It is recommended to use 5.1 ohm + a
1uF ceramic cap acitor for V
DDQ
p in's filter to increase the noise immunity.
The AV
CC
p in is used to sup p ly all of the internal control circuitry. AV
CC
voltage
h as to b e greater th an i ts U V LO th resh ol d vol tage ( 2.1V ty p i cal ) to al l ow th e
SC2595 b e in normal op eration. If AV
CC
voltage is lower than the UV LO threshold
voltage, the V
TT
outp ut voltage will remain at 0V.
The PV
CC
p in p rovides the rail voltage from where the V
TT
p in draws load current.
There is a limitation b etween AV
CC
and PV
CC
. The PV
CC
voltage must b e less or
eq ual to AV
CC
voltage to ensure the correct outp ut voltage regulation. The V
TT
source current cap ab ility is dep endent on PV
CC
voltage. Higher the voltage on
PV
CC
, higher the source current; however, it will cause more p ower loss and higher
temp erature rise [figure 5, 11, 12].
The V
TT
p in is the outp ut of SC2595. It can sink and source 1.5A continuous
cu rren t an d 3A p eak cu rren t w h i l e k eep i n g ex cel l en t l oad reg u l at i on . I t i s
recommen d ed th at on e sh ou l d u se at l east 220u F l ow E SR cap aci tors ( E SR
sh ou l d b e l ow er t h an 250m oh m) an d 10u F cerami c cap aci t ors, w h i ch are
uniformly sp read on the V
TT
strip p lane to reduce the voltage sp ike under load
transient condition.
Thermal p ad should b e connected to GN D.
(1)
PRELIMINARY
P i n Fu n c t i o n
4
V REF
5
V DDQ
(2)
6
AV CC
(2)
7
PV CC
(2)
8
V TT
Thermal
Pad
©2009
Semtech Corp.
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