EDI88512CA-XMXG
WPS512K8X-XRJXG
512Kx8 Plastic Monolithic SRAM CMOS
FEATURES
512Kx8 bit CMOS Static
Random Access Memory
• Access Times of 17, 20, 25ns
• Data Retention Function (LPA version)
• Extended Temperature Testing
• Data Retention Functionality Testing
36 lead JEDEC Approved Revolutionary Pinout
• Plastic SOJ (Package 319)
Single +5V (±10%) Supply Operation
RoHS compliant
WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to
capitalize on the cost advantage of using a plastic component while
not sacrificing all of the reliability available in a full military device.
Extended temperature testing is performed with the test patterns
developed for use on WEDC’s fully compliant 512Kx8 SRAMs.
WEDC fully characterizes devices to determine the proper test
patterns for testing at temperature extremes. This is critical because
the operating characteristics of device change when it is operated
beyond the commercial guarantee a device that operates reliably
in the
fi
eld at temperature extremes. Users of WEDC’s ruggedized
plastic benefit from WEDC’s extensive experience in characterizing
SRAMs for use in military systems.
WEDC ensures Low Power devices will retain data in Data
Retention mode by characterizing the devices to determine the
appropriate test conditions. This is crucial for systems operating
at -40°C or below and using dense memories such as 512Kx8s.
WEDC’s ruggedized plastic SOJ is footprint compatible with
WEDC’s full military ceramic 36 pin SOJ.
FIGURE 1 – PIN CONFIGURATION
TOP VIEW
PIN Description
I/O
0-7
A
0-18
WE#
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
A0
A1
A2
A3
A4
CS#
I/O0
I/O1
V
CC
V
SS
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36pin
Revolutionary
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE#
I/O7
I/O6
V
SS
V
CC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
CS#
OE#
V
CC
V
SS
NC
Not Connected
BLOCK DIAGRAM
Memory Array
A
Ø-18
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
Ø-7
WE#
CS#
OE#
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 11
© 2014 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA-XMXG
WPS512K8X-XRJXG
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
0 to +70
-40 to +85
-55 to +125
-65 to +150
1.5
20
175
°C
°C
°C
°C
W
mA
°C
-0.5 to 7.0
Unit
V
OE#
X
H
L
X
CS#
H
L
L
L
WE#
X
H
H
L
TRUTH TABLE
Mode
Standby
Output Deselect
Read
Write
Output
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc1
Icc1
Icc1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.0
-0.5
Typ
5.0
0
—
—
Max
5.5
0
V
CC
+ 0.5
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions greater than
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAPACITANCE
T
A
= +25°C
Parameter
Address Lines
Data Lines
Symbol
CI
CO
Condition
VIN = Vcc or Vss, f = 1.0MHz
VIN = Vcc or Vss, f = 1.0MHz
Max
8
8
Unit
pF
pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
V
CC
= 5V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output High Volltage
Output Low Voltage
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
-0.3V
Symbol
I
LI
I
LO
I
CC
I
SB
V
OH
V
OL
Conditions
V
CC
= 5.5, V
IN
= V
SS
to V
CC
CS# = V
IL
, OE# = V
IH
, V
OUT
= V
SS
to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OH
= -4.0mA, V
CC
= 4.5
I
OL
= 8.0mA, V
CC
= 4.5
Min
Max
10
10
180
15
Units
μA
μA
mA
mA
V
V
2.4
0.4
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
480Ω
480Ω
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF (Figure 2)
V
SS
to 3.0V
5ns
1.5V
Figure 1
Q
255Ω
30pF
Q
255Ω
5pF
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 11
© 2014 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA-XMXG
WPS512K8X-XRJXG
AC CHARACTERISTICS – READ CYCLE
V
CC
= 5.0V, V
SS
= 0V, 0°C
≤
T
A
≤
+70°C
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
1. This parameter is guaranteed by design but not tested.
Symbol
JEDEC
Alt.
t
AVAV
t
AVQV
t
ELQV
t
ELQX
t
EHQZ
t
AVQX
t
GLQV
t
GLQX
t
GHQZ
t
RC
t
AA
t
ACS
t
CLZ
t
CHZ
t
OH
t
OE
t
OLZ
t
OHZ
Min
17
17ns
Max
17
17
Min
20
20ns
Max
20
20
Min
25
25ns
Max
25
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
0
0
8
0
0
7
7
3
0
0
10
0
0
8
8
3
0
0
12
0
0
10
10
AC CHARACTERISTICS – WRITE CYCLE
V
CC
= 5.0V, V
SS
= 0V, 0°C
≤
T
A
≤
+70°C
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
1. This parameter is guaranteed by design but not tested.
Symbol
JEDEC
Alt.
t
AVAV
t
ELWH
t
ELEH
t
AVWL
t
AVEL
t
AVWH
t
AVEH
t
WLWH
t
WLEH
t
WHAX
t
EHAX
t
WHDX
t
EHDX
t
WLQZ
t
DVWH
t
DVEH
t
WHQX
t
WC
t
CW
t
CW
t
AS
t
AS
t
AW
t
AW
t
WP
t
WP
t
WR
t
WR
t
DH
t
DH
t
WHZ
t
DW
t
DW
t
WLZ
Min
17
14
14
0
0
14
14
14
14
0
0
0
0
0
8
8
0
17ns
Max
Min
20
15
15
0
0
15
15
15
15
0
0
0
0
20ns
Max
Min
25
17
17
0
0
17
17
17
17
0
0
0
0
25ns
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
0
10
10
0
8
0
12
12
0
10
ns
ns
ns
ns
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 11
© 2014 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA-XMXG
WPS512K8X-XRJXG
FIGURE 2 – TIMING WAVEFORM — READ CYCLE
t
AVAV
ADDRESS
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
t
AVQV
CS#
t
AVQV
DATA I/O
t
AVQX
OE#
DATA 1
DATA 2
t
ELQV
t
ELQX
t
GLQV
t
GLQX
DATA OUT
t
EHQZ
t
GHQZ
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE — WE# CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS#
t
WHAX
t
AVWL
WE#
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE — CS# CONTROLLED
t
AVAV
ADDRESS
t
AVEH
t
ELEH
CS#
t
EHAX
t
AVEL
WE#
t
WLEH
t
DVEH
t
EHDX
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 11
© 2014 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA-XMXG
WPS512K8X-XRJXG
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)
-55°C
≤
T
A
≤
+125°C
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
V
DD
I
CCDR
T
CDR
T
R
Conditions
V
DD
= 2.0V
CS#
≥
V
DD
-0.2V
V
IN
≥
V
DD
-0.2V
or V
IN
≤
0.2V
Min
2
–
0
T
AVAV
Typ
–
–
–
Max
–
15
–
–
Units
V
mA
ns
ns
FIGURE 5 – DATA RETENTION — CS# CONTROLLED
Data Retention Mode
Vcc
4.5V
V
DD
4.5V
t
CDR
CS#
CS# = V
DD
-0.2V
t
R
DATA RETENTION, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014
Rev. 11
© 2014 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
PCB Design
京公网安备 11010802033920号
EEWORLD
