MT48LC16M16A2P-6A:G TR datasheet, PDF

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MT48LC16M16A2P-6A:G TR: DescriptionDRAM Chip SDR SDRAM 256Mbit 16Mx16 3.3V 54-Pin TSOP-II T/R; File Size1MB，94 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT48LC16M16A2P-6A:G TR Overview

DRAM Chip SDR SDRAM 256Mbit 16Mx16 3.3V 54-Pin TSOP-II T/R

MT48LC16M16A2P-6A:G TR Parametric

Parameter Name	Attribute value
EU restricts the use of certain hazardous substances	Compliant
ECCN (US)	EAR99
Part Status	Active
HTS	8542.32.00.24
DRAM Type	SDR SDRAM
Chip Density (bit)	256M
Organization	16Mx16
Number of Internal Banks	4
Number of Words per Bank	4M
Number of Bits/Word (bit)	16
Data Bus Width (bit)	16
Maximum Clock Rate (MHz)	167
Maximum Access Time (ns)	17\|7.5\|5.4
Address Bus Width (bit)	15
Process Technology	CMOS
Interface Type	LVTTL
Minimum Operating Supply Voltage (V)	3
Typical Operating Supply Voltage (V)	3.3
Maximum Operating Supply Voltage (V)	3.6
Operating Current (mA)	100
Minimum Operating Temperature (°C)	0
Maximum Operating Temperature (°C)	70
Supplier Temperature Grade	Commercial
Number of I/O Lines (bit)	16
Supplier Package	TSOP-II
Pin Count	54
Mounting	Surface Mount
Package Height	1(Max)
Package Length	22.22
Package Width	10.16
PCB changed	54

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256Mb: x4, x8, x16 SDRAM

Features

SDR SDRAM

MT48LC64M4A2 – 16 Meg x 4 x 4 banks

MT48LC32M8A2 – 8 Meg x 8 x 4 banks

MT48LC16M16A2 – 4 Meg x 16 x 4 banks

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 8192-cycle refresh (commercial and

industrial)

– 16ms, 8192-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

Options

• Configurations

– 64 Meg x 4 (16 Meg x 4 x 4 banks)

– 32 Meg x 8 (8 Meg x 8 x 4 banks)

– 16 Meg x 16 (4 Meg x 16 x 4 banks)

• Write recovery (

WR)

–

WR = 2 CLK

• Plastic package – OCPL

– 54-pin TSOP II OCPL

(400 mil)

(standard)

– 54-pin TSOP II OCPL

(400 mil)

Pb-free

– 60-ball TFBGA (x4, x8) (8mm x

16mm)

– 60-ball TFBGA (x4, x8) (8mm x

16mm) Pb-free

– 54-ball VFBGA (x16) (8mm x 14 mm)

Pb-free

– 54-ball VFBGA (x16) (8mm x 8 mm)

Pb-free

• Timing – cycle time

– 6ns @ CL = 3 (x8, x16 only)

– 7.5ns @ CL = 3 (PC133)

– 7.5ns @ CL = 2 (PC133)

• Self refresh

– Standard

– Low power

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Revision

Notes:

Off-center parting line.

Only available on Revision D.

Only available on Revision G.

Contact Micron for availability.

Marking

64M4

32M8

16M16

-6A

-75

-7E

None

:D/:G

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. W 05/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

256Mb: x4, x8, x16 SDRAM

Features

Contents

Important Notes and Warnings ......................................................................................................................... 8

General Description ......................................................................................................................................... 8

Automotive Temperature .............................................................................................................................. 9

Functional Block Diagrams ............................................................................................................................. 10

Pin and Ball Assignments and Descriptions ..................................................................................................... 13

Package Dimensions ....................................................................................................................................... 17

Temperature and Thermal Impedance ............................................................................................................ 21

Electrical Specifications .................................................................................................................................. 25

Electrical Specifications – I

Parameters ........................................................................................................ 27

Electrical Specifications – AC Operating Conditions ......................................................................................... 29

Functional Description ................................................................................................................................... 32

Commands .................................................................................................................................................... 33

COMMAND INHIBIT .................................................................................................................................. 33

NO OPERATION (NOP) ............................................................................................................................... 34

LOAD MODE REGISTER (LMR) ................................................................................................................... 34

ACTIVE ...................................................................................................................................................... 34

READ ......................................................................................................................................................... 35

WRITE ....................................................................................................................................................... 36

PRECHARGE .............................................................................................................................................. 37

BURST TERMINATE ................................................................................................................................... 37

REFRESH ................................................................................................................................................... 38

AUTO REFRESH ..................................................................................................................................... 38

SELF REFRESH ....................................................................................................................................... 38

Truth Tables ................................................................................................................................................... 39

Initialization .................................................................................................................................................. 44

Mode Register ................................................................................................................................................ 46

Burst Length .............................................................................................................................................. 48

Burst Type .................................................................................................................................................. 48

CAS Latency ............................................................................................................................................... 50

Operating Mode ......................................................................................................................................... 50

Write Burst Mode ....................................................................................................................................... 50

Bank/Row Activation ...................................................................................................................................... 51

READ Operation ............................................................................................................................................. 52

WRITE Operation ........................................................................................................................................... 61

Burst Read/Single Write .............................................................................................................................. 68

PRECHARGE Operation .................................................................................................................................. 69

Auto Precharge ........................................................................................................................................... 69

AUTO REFRESH Operation ............................................................................................................................. 81

SELF REFRESH Operation ............................................................................................................................... 83

Power-Down .................................................................................................................................................. 85

Clock Suspend ............................................................................................................................................... 86

Revision History ............................................................................................................................................. 89

Rev. W – 05/15 ............................................................................................................................................ 89

Rev. W – 09/14 ............................................................................................................................................ 89

Rev. V – 1/14, 8/14 ...................................................................................................................................... 89

Rev. U – 05/13 ............................................................................................................................................. 89

Rev. T – 03/13 ............................................................................................................................................. 89

Rev. S – 12/12 ............................................................................................................................................. 89

Rev. R – 10/12 ............................................................................................................................................. 89

Rev. Q – 02/12 ............................................................................................................................................. 89

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. W 05/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

256Mb: x4, x8, x16 SDRAM

Features

Rev. P – 12/11 .............................................................................................................................................

Rev. O – 07/11 .............................................................................................................................................

Rev. N – 01/10 .............................................................................................................................................

Rev. M – 11/08 ............................................................................................................................................

Rev. L – 08/07 .............................................................................................................................................

Rev. K – 02/07 .............................................................................................................................................

Rev. K – 06/06 .............................................................................................................................................

Rev. J – 03/05 ..............................................................................................................................................

Rev. H – 02/05 .............................................................................................................................................

Rev. H – 10/04 .............................................................................................................................................

Rev. G – 08/03 .............................................................................................................................................

Rev. F – 01/03 .............................................................................................................................................

Rev. E – 03/02 .............................................................................................................................................

Rev. D – 07/01 .............................................................................................................................................

Rev. C – 03/01 .............................................................................................................................................

Rev. B – 10/00 .............................................................................................................................................

Rev. A – 11/99 .............................................................................................................................................

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. W 05/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

256Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 64 Meg x 4 Functional Block Diagram ...............................................................................................

Figure 2: 32 Meg x 8 Functional Block Diagram ...............................................................................................

Figure 3: 16 Meg x 16 Functional Block Diagram .............................................................................................

Figure 4: 54-Pin TSOP (Top View) ..................................................................................................................

Figure 5: 60-Ball FBGA (Top View) .................................................................................................................

Figure 6: 54-Ball VFBGA (Top View) ...............................................................................................................

Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ...............................................................................................

Figure 8: 60-Ball TFBGA "BB/FB" (8mm x 16mm) (x4, x8) ...............................................................................

Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) ..................................................................................

Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ...................................................................................

Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ...............................................

Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................

Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) ..............................................

Figure 14: ACTIVE Command ........................................................................................................................

Figure 15: READ Command ...........................................................................................................................

Figure 16: WRITE Command .........................................................................................................................

Figure 17: PRECHARGE Command ................................................................................................................

Figure 18: Initialize and Load Mode Register ..................................................................................................

Figure 19: Mode Register Definition ...............................................................................................................

Figure 20: CAS Latency ..................................................................................................................................

Figure 21: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 ..........................................................

Figure 22: Consecutive READ Bursts ..............................................................................................................

Figure 23: Random READ Accesses ................................................................................................................

Figure 24: READ-to-WRITE ............................................................................................................................

Figure 25: READ-to-WRITE With Extra Clock Cycle .........................................................................................

Figure 26: READ-to-PRECHARGE ..................................................................................................................

Figure 27: Terminating a READ Burst .............................................................................................................

Figure 28: Alternating Bank Read Accesses .....................................................................................................

Figure 29: READ Continuous Page Burst .........................................................................................................

Figure 30: READ – DQM Operation ................................................................................................................

Figure 31: WRITE Burst .................................................................................................................................

Figure 32: WRITE-to-WRITE ..........................................................................................................................

Figure 33: Random WRITE Cycles ..................................................................................................................

Figure 34: WRITE-to-READ ............................................................................................................................

Figure 35: WRITE-to-PRECHARGE .................................................................................................................

Figure 36: Terminating a WRITE Burst ............................................................................................................

Figure 37: Alternating Bank Write Accesses .....................................................................................................

Figure 38: WRITE – Continuous Page Burst .....................................................................................................

Figure 39: WRITE – DQM Operation ...............................................................................................................

Figure 40: READ With Auto Precharge Interrupted by a READ .........................................................................

Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................

Figure 42: READ With Auto Precharge ............................................................................................................

Figure 43: READ Without Auto Precharge .......................................................................................................

Figure 44: Single READ With Auto Precharge ..................................................................................................

Figure 45: Single READ Without Auto Precharge .............................................................................................

Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................

Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ......................................................................

Figure 48: WRITE With Auto Precharge ...........................................................................................................

Figure 49: WRITE Without Auto Precharge .....................................................................................................

Figure 50: Single WRITE With Auto Precharge .................................................................................................

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. W 05/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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