P4C168, P4C169, P4C170
P4C168, P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25ns (Commercial)
– 20/25/35ns (P4C168 Military)
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Single 5V
±
10% Power Supply
Fully TTL Compatible, Common I/O Ports
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ and SOIC
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of 16,384-
bit ultra high-speed static RAMs organized as 4K x 4. All
three devices have common input/output ports.The
P4C168 enters the standby mode when the chip enable
(CE) control goes high; with CMOS input levels, power
consumption is only 83mW in this mode. Both the P4C169
and the P4C170 offer a fast chip select access time that is
only 67% of the address access time. In addition, the
P4C170 includes an output enable (OE) control to elimi-
nate data bus contention. The RAMs operate from a single
5V
±
10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
The P4C168 and P4C169 are available in 20-pin (P4C170
in 22-pin) 300 mil DIP packages providing excellent board
level densities. The P4C168 is also available in 20-pin 300
mil SOIC and SOJ packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package. The P4C170 is also available in a 22-pin 300 mil
SOJ package.
FUNCTIONAL BLOCK DIAGRAM
A
ROW
SELECT
A
16,384-BIT
MEMORY
ARRAY
PIN CONFIGURATIONS
(7)
A
0
A
1
A
2
INPUT
DATA
CONTROL
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
A
11
A
10
A
9
A
8
I/O
4
I/O
3
I/O
2
I/O
1
WE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CS
OE
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
A
11
A
10
A
9
A
8
NC
I/O
4
I/O
3
I/O
2
I/O
1
WE
I/O
1
I/O
2
I/O
3
I/O
4
COLUMN I/O
A
3
A
4
A
5
A
6
A
7
CE, CS
GND
POWER
DOWN
COLUMN
SELECT
CE or CS
WE
OE
NOTES:
CE
USED ON P4C168 ALSO FOR POWER DOWN FUNCTIONS
CE
USED ON P4C169 FAST CHIP SELECT
OE
OUTPUT ENABLE FUNCTION ON P4C170 ONLY
P4C168
ONLY
A
(5)
A
P4C168
P4C169
DIP (P2, D2) DIP (P2)
SOIC (S2)
SOIC (S2)
SOJ (J2)
TOP VIEW
P4C170
DIP (P3)
TOP VIEW
Means Quality, Service and Speed
1Q97
33
P4C168, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC§
t
AC‡
t
OH
t
LZ‡
t
HZ†
t
OE†
t
OLZ†
t
OHZ†
t
RCS
t
RCH
t
PU§
t
PD§
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Select Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Data Valid
Output Enable to Output in Low Z
Output Disable to Output in High Z
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
0
0
0
0
2
2
–12
12
12
12
8
2
2
6
8
0
6
0
0
0
12
–15
15
15
15
9
2
2
7
10
0
7
0
0
0
15
–20
20
20
20
12
2
2
9
12
0
9
0
0
0
20
–25
–35
Unit
ns
Min Max Min Max Min Max Min Max Min Max
25
25
25
15
2
2
10
15
0
11
0
0
0
25
35
15
15
15
35
35
35
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)
(5,6)
(9)
t
RC
ADDRESS
t
AA
t
OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE/CS
and
OE
are LOW for READ cycle.
35
P4C168, P4C169, P4C170
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE
CS
CONTROLLED)
(5,7)
CE/CS
CE
READ CYCLE WAVEFORM NO. 2 (CS Controlled)
t
RC
CE/CS
(7)
(5,7)
t
AC
DATA VALID
t
OLZ
(7)
t
HZ
(7)
t
LZ
DATA OUT
HIGH IMPEDANCE
(7)
t
OHZ
t
OE
OE
(P4C170)
t
RCS
WE
I
CC
V
CC
SUPPLY
CURRENT
(P4C168 ONLY)
I
SB
t
PU
t
PD
t
RCH
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE CONTROLLED)
(5)
OE
(9)
t
RC
ADDRESS
t
AA
OE
t
OE
(8)
t
OH
t
OLZ
CS
AC
(8)
t
LZ
t
t
(8)
OHZ
(8)
t
HZ
DATA OUT
Notes:
7. ADDRESS must be valid prior to, or coincident with
CE/CS
transition
low. For Fast
CS,
t
AA
must still be met.
8. Transition is measured
±200mV
from steady state voltage prior to
change, with loading as specified in Figure 1.
1521 05
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
36
P4C168, P4C169, P4C170
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to
End of Write
Address Valid to
End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
0
–12
12
12
12
0
12
0
7
0
4
0
–15
15
15
15
0
15
0
8
0
5
0
–20
18
18
18
0
18
0
10
0
7
0
–25
20
20
20
0
20
0
10
0
7
0
–35
35
30
30
0
30
0
15
0
13
Min Max Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(10)
WE
t
WC
ADDRESS
t
CW
CE/CS
t
AW
t
WP
WE
t
AS
DATA IN
t
WZ
DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
(8)
(12)
t
WR
t
AH
t
DW
DATA VALID
t
DH
t
OW
(8,11)
Notes:
10.
CE/CS
and
WE
must be LOW for WRITE cycle.
11. If
CE/CS
goes HIGH simultaneously with
WE
HIGH, the output
remains in a high impedance state.
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
37
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
