IP1718 LF
Preliminary Data Sheet
18-port 10/100Mbps Smart Switch Controller
Features
Embeds 1.5 Mb packet buffer
Handles up to 4K MAC address entries
Supports non-blocking wire speed operation
Provides 16-port SS-SMII and 2-port MII
Supports 2 ports selectable normal MII,
reverse MII
All I/O signals can operate at 3.3V or 1.8V.
Supports up to 18 port based VLAN group
Supports 256 levels of data rate control
Captures BPDU, IGMP and OSPF …packet
and forward to the CPU port.
Suppress/enable per port address learning.
Embeds two levels of priority queues for VLAN
tag, physical port and IP Differentiated Service.
Supports flexible port trunking configuration: up
to 3 groups and up to 4 ports for each group
Embeds an internal regulator controller to
simplify the system design.
Power supply: 1.8V for core logic; optional
3.3V or 1.8V for I/O.
128 pin QFP package
Adjustable I/O driving capability
Support packet length up to 1536 Bytes
Spanning Tree state support.
Supports 3 kinds of port mirrioring methods
HOL blocking prevention
Only one 25MHz crystal needed
Broadcast storm control support
Programmable MAC address table through 2
serial pins.
Support Lead Free package (Please refer to
the Order Information)
General Description
Supporting 16-port SS-SMII, 2-port MII and
various advanced features, the IP1718 LF fits both
the office switch and the ETTH( Ethernet to the
Home) application. The IP1718 LF embeds
internal SSRAM for the use of the packet buffer
and the MAC address table. Besides the
traditional switch functions, the IP1718 LF
provides the easy-to-design solution, fitting the
requirement of most switch application.
The IP1718 LF also supports some features which
can simplify the customer’s design from the
viewpoint of the system. The embedded regulator
controller can reduce the component number on
the system board. The web management can be
easily accomplished by adding an external CPU
with protocol stack. All the I/O pins can operate at
3.3V or 1.8V, providing more design flexibility for
power supply distribution.
The IP1718 LF embeds 1.5Mb internal packet
buffer and stores up to 4K MAC address entries,
making it suitable for the generic switch
application. In addition, the IP1718 LF supports a
wide range of data rate for both egress and
ingress, which is useful in the ETTH(Ethernet to
the Home) application. The higher layer data
packet such as BPDU, IGMP, OSPF can be
forwarded to either the 17
th
or 18
th
(CPU) port. The
flexible trunk configuration allows the user to scale
the switch interconnection bandwidth. When the
port mirroring function is enabled, the data traffic
on the source port will be forwarded to a specified
destination port, making the switch administration
easier. Supporting up to 18 port based VLAN
groups, the IP1718 LF can be configured to fit
various traffic partitions. The CoS function is
accomplished by configuring the priority of the
physical port, the 802.1Q VLAN tag and IP
DSCP(Differentiated Service Code Point). In order
to fit the application of some special environment,
the address learning and the MAC address table
aging can be disabled.
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Copyright © 2003, IC Plus Corp.
January 27, 2005
IP1718 LF-DS-R05
IP1718 LF
Preliminary Data Sheet
Table Of Contents
Features .................................................................................................................................................................. 1
General Description................................................................................................................................................. 1
Table Of Contents.................................................................................................................................................... 2
Revision History....................................................................................................................................................... 3
1 Pin Diagram...................................................................................................................................................... 4
2 Block Diagram .................................................................................................................................................. 5
3 Pin description.................................................................................................................................................. 6
Pin description (continued)...................................................................................................................................... 7
Pin description (continued)...................................................................................................................................... 9
Pin description (continued).................................................................................................................................... 10
4 Functional Description.................................................................................................................................... 11
4.1
Medium Access Control(MAC)........................................................................................................... 11
4.1.1
Data Rate Control ................................................................................................................. 11
4.1.2
Flow Control.......................................................................................................................... 11
4.2
Switch Engine and Queue Management ........................................................................................... 12
4.2.1
Store & Forward Mechanism ................................................................................................ 12
4.2.2
Address Learning and aging time ......................................................................................... 12
4.2.3
Class of Service .................................................................................................................... 12
4.2.4
Port_based VLAN ................................................................................................................. 13
4.2.5
Trunk Channel ...................................................................................................................... 14
4.2.6
Port Mirroring ........................................................................................................................ 14
4.2.7
Queue Management ............................................................................................................. 14
4.2.8
Broadcast Storm Control....................................................................................................... 15
4.2.9
Handling the Higher Layer Protocol...................................................................................... 15
4.2.10
Port Security ......................................................................................................................... 15
5 System Operation .......................................................................................................................................... 16
5.1
Reset and EEPROM Download Procedure ....................................................................................... 16
5.2
Polling/Writing the PHY...................................................................................................................... 16
5.3
Programming the Internal Registers .................................................................................................. 17
5.4
SS-SMII.............................................................................................................................................. 17
6 Register Map .................................................................................................................................................. 19
7 Electrical Characteristics................................................................................................................................ 28
7.1
Absolute Maximum Rating................................................................................................................. 28
7.2
AC Characteristics ............................................................................................................................. 28
7.3
DC Characteristics ............................................................................................................................. 31
8 Order Information ........................................................................................................................................... 32
9 Package Detail ............................................................................................................................................... 33
2/33
Copyright © 2003, IC Plus Corp.
January 27, 2005
IP1718 LF-DS-R05
Industrial Control Electronics
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