SY0004-1.544-19.44-77.76-1.544 datasheet, PDF

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> SY0004-1.544-19.44-77.76-1.544

SY0004-1.544-19.44-77.76-1.544: DescriptionSupport Circuit, 1-Func, 3.90 X 2.40 INCH, 0.90 INCH HEIGHT, PACKAGE-24; CategoryWireless rf/communication Telecom circuit; File Size101KB，5 Pages; ManufacturerRaltron; Websitehttp://www.raltron.com/

Download Datasheet Parametric View All

SY0004-1.544-19.44-77.76-1.544 Overview

Support Circuit, 1-Func, 3.90 X 2.40 INCH, 0.90 INCH HEIGHT, PACKAGE-24

SY0004-1.544-19.44-77.76-1.544 Parametric

Parameter Name	Attribute value
Maker	Raltron
package instruction	,
Reach Compliance Code	compliant
JESD-30 code	R-XDMA-P24
length	99.06 mm
Number of functions	1
Number of terminals	24
Maximum operating temperature	60 °C
Minimum operating temperature	-20 °C
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
Nominal supply voltage	5 V
surface mount	NO
Telecom integrated circuit types	ATM/SONET/SDH SUPPORT CIRCUIT
Temperature level	OTHER
Terminal form	PIN/PEG
Terminal pitch	7.62 mm
Terminal location	DUAL
width	60.96 mm

Preview

Download Datasheet

View All

SYNCHRONOUS EQUIPMENT CLOCK

STRATUM 3E CLOCK UNIT – SY0004

Model SY0004

Date: March 21-00

PRELIMINARY

•

INTRODUCTION

The SY-0004 is an accurate time and frequency source that has been designed as a module level subsystem. The

module is designed to work within ATM, SONET, SDH, and wireless systems where synchronization is vital. The

SY-0004 is an excellent synchronization solution for timing, jitter and wander topics specified within ITU-T

Recommendations G.812, and Bellcore GR-1244-CORE. The SY-0004 is designed for Stratum 3E applications,

but also has certain features that can make it useful for other kinds of system clocks.

•

FEATURES

A synchronization solution for timing, jitter and wander concerns in a single module.

Complies with ITU-T Recommendations G.812 - Type III and Bellcore GR-1244-CORE for Stratum 3E

applications.

Supports four modes of operation: Locked to Reference 1, Locked to Reference 2, Holdover and Free-run.

Accepts reference inputs from two independent sources from 8 kHz to 77.76 MHz.

Provides two outputs up to 77.76 MHz and one up to 2.048MHz.

Loop filtering utilizing application specific software in the digital signal processor (DSP).

Continuously monitors and evaluate input reference signals.

Creates a history buffer for Holdover mode operation.

Manual or Automatic selection between timing modes.

Alarm and status signal.

Host interface and JTAG port.

Small dimensions of 3.9 x 2.4 x 0.9 inch.

•

APPLICATION

The SY-0004 performs clock regeneration as a Synchronous Equipment Clock (SEC), or STRATUM 3E in ATM,

SDH, PDH, and SONET networks. It is designed for manufacturers of network equipment, especially Access

Switches, Core Switches, Cross Connects, Digital Multiplexers-Exchangers, and SDH/SONET equipment. The unit

is also suitable for PCS, WLL, and Wireless Base Stations. Wherever a Timing unit with high performance

specifications is required, the SY0004 can be integrated into the network system and provide all necessary

frequencies and interfaces. The input stage can receive two different input reference signals at various rates from

4 kHz to 77.76 MHz. An optional application can be achieved by integrating the SY0004 with a low cost GPS

receiver and locking it to the GPS 1 pps output signal.

RALTRON ELECTRONICS CORP.

10651 N.W.19 St

Florida 33172

U.S.A.

Tel: 305 593-6033

Fax: 305-594-3973

e-mail: sales@raltron.com

Internet: http:/www.raltron.com

SYNCHRONOUS EQUIPMENT CLOCK

STRATUM 3E CLOCK UNIT – SY0004

Alarms and Statuses

T.S

OCXO

Ex.Ref.1 1

Ex.Ref.2

MUX,

FPD,

Counters

Logic

OUT 3

DSP

(RAM,

FLASH)

DDS

Output

PLL

Synthesizer

OUT 2

OUT 1

Control Inputs

SPI

JTAG

Figure 1. - The functional block diagram of SY0004

•

DESCRIPTION

The SY0004 synchronization module is a Digital PLL (DPLL), which utilizes application specific software in the

digital signal processor (DSP). The DSP is complemented by fast hardware logic (CPLD) where all multiplexers,

counters, dividers, phase detectors, output frequency converters and other control logic circuits are completely

implemented. The module uses Direct Digital Synthesis (DDS) technique combine with high stability OCXO in

order to provide accurate and fast response in the DPLL and eliminate requirements for an OCXO with high pull.

The output of the DDS is connected to an output PLL synthesizer that generates two output signals. The third

output comes from DDS. The SY0004 provides several other features such as: switching between the references

inputs on the basis of monitoring and estimation of the input signals and internal state diagram; real time

calculation of the filtering algorithm for jitter and wander in according to the approved standards; alarm, status and

messaging functions; controlling the internal references in regard of frequency vs. temperature (utilizing

temperature measurement with T.S.), aging and calibration effects etc. The three wires serial communication

interface - SPI provides flow of messages between the module and host computer. The JTAG interface provides

an easy way for re-programming the unit with future versions of software without removing from the systems.

The module operates in the following four timing modes:

Free-run

In this mode the unit is unlocked to either of the inputs. The accuracy of the output frequencies in this mode is

±4.6ppm. Free-run mode is typically used when a master clock source is required, not valid history of data for the

Holdover mode, or immediately following system power-up before network synchronization is achieved. In the

Free-run Mode, the SY0004 provides timing and synchronization signals that are based on the accuracy of on-

board oscillators only, and are not synchronized to the reference signals.

Holdover

In this mode the module has lost its reference inputs and is utilizing stored timing data, called history, to control the

output frequency. Holdover Mode is typically used while network synchronization is temporarily disrupted. In

Holdover Mode, the SY0004 provides timing, based on data from the history buffer, while unlocked to an external

reference signal. The history data is determined while the device is locked to an external reference signal. The

stability of the output signal in holdover mode depends primarily on the stability of on-board oscillator and should

be better then 10ppb in the first 24 hours. The SY0004 uses an OCXO as an on-board oscillator but other types of

oscillators are available.

Locked to Ref.1

In this mode the output of the module is phase locked to input reference 1.

RALTRON ELECTRONICS CORP.

10651 N.W.19 St

Florida 33172

U.S.A.

Tel: 305 593-6033

Fax: 305-594-3973

e-mail: sales@raltron.com

Internet: http:/www.raltron.com

Recommended Resources

CMOS and industrial control interface circuit

Interlock control circuit of drilling machine spindle motor and hydraulic motor

Reverse polarity drive circuit

24V VMOS tube regulated power supply circuit

Application of IR2110 in three-phase bridge motor drive circuit

Computer motherboard circuit diagram 820 1_32

How to use IAR for 430 software for beginners: The software used by the msp430 microcontroller is IAR software. The following describes how to create a new workspace and project in IAR software. workspace workspace, which can store multiple projec...; 灞波儿奔 Microcontroller MCU

[RISC-V MCU CH32V103 Review] ---Advancing Dimension---Unboxing: [RISC-V MCU CH32V103 Review] ---Advancing Dimension---UnboxingThe Advancement of Victory January 20 ,2021 1. IntroductionThis article will Introduce several stages of C language compilation (please sk...; wintonson Domestic Chip Exchange

How to solve the strange phenomenon of CCS: 1. SummaryCode Composer Studio (CCSv5, CCSv6, CCSv7) based on the Eclipse open source framework sometimes displays abnormalities during use, such as missing menus or frequent crashes. These abnormalit...; 火辣西米秀 Microcontroller MCU

Disassembly report | Honor X20 SE + OPPO A74 + Redmi Note 10 Pro: Disassembly previewHonor X20 SE — Nanxin SC8545 insideOPPO A74 overseas version — Nanxin SC8547 insideRedmi Note 10 Pro — Nanxin SC8551A inside01Honor X20 SE TeardownOn July 9, the new HONOR X20 SE we...; 木犯001号 Power technology

USART_SendArray(DEBUG_USARTx, a,10); failed to output the elements in a[10]?: [align=left][font=仿宋][size=16pt][font=仿宋]In the serial port test, [/font]USART_SendArray(DEBUG_USARTx, a,10); failed to output the elements in a[10]? The following program is written in the example, #...; csz9981 stm32/stm8

MSP430F149 clock program architecture: [size=4]Program architecture[/size] [size=4] [/size] [size=4] Generally, the system clock needs to be configured after the watchdog is turned off after system initialization. The configuration steps a...; fish001 Microcontroller MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components