EPM7256ATC100-6 datasheet, PDF

EPM7256ATC100-6: DescriptionEE PLD, 6ns, 256-Cell, CMOS, PQFP100, TQFP-100; CategoryProgrammable logic devices Programmable logic; File Size1MB，66 Pages; ManufacturerAltera (Intel)

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EPM7256ATC100-6 Overview

EE PLD, 6ns, 256-Cell, CMOS, PQFP100, TQFP-100

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	QFP
package instruction	LFQFP, TQFP100,.63SQ
Contacts	100
Reach Compliance Code	compli
Other features	256 MACROCELLS; 16 LABS; CONFIGURABLE I/O OPERATION WITH 2.5V OR 3.3V
maximum clock frequency	156.3 MHz
In-system programmable	YES
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
JTAG BST	YES
length	14 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	84
Number of macro cells	256
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 84 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	TQFP100,.63SQ
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	220
power supply	2.5/3.3,3.3 V
Programmable logic type	EE PLD
propagation delay	6 ns
Certification status	Not Qualified
Maximum seat height	1.27 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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