EM488M3244LBB-7FE datasheet, PDF

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EM488M3244LBB-7FE: Description256Mb (2MÃ4BankÃ32) Synchronous DRAM; File Size319KB，19 Pages; ManufacturerEOREX; Websitehttp://www.eorex.com

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EM488M3244LBB-7FE Overview

256Mb (2MÃ4BankÃ32) Synchronous DRAM

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eorex

Features

Preliminary

EM488M3244LBB

256Mb (2M

4Bank

32) Synchronous DRAM

Description

The EM488M3244LBB is Synchronous Dynamic

Random Access Memory (SDRAM) organized as

2Meg words x 4 banks by 32 bits. All inputs and

outputs are synchronized with the positive edge of

the clock.

The 256Mb SDRAM uses synchronized pipelined

architecture to achieve high speed data transfer

rates and is designed to operate at 1.8V low power

memory system. It also provides auto refresh with

power saving / down mode. All inputs and outputs

voltage levels are compatible with LVCMOS.

Available packages: BGA-90B (13mmx8mm)

• Fully Synchronous to Positive Clock Edge

• Single 1.8V

±0.1V

Power Supply

• LVCMOS Compatible with Multiplexed Address

• Programmable Burst Length (B/L) - 1, 2, 4, 8

or Full Page

• Programmable CAS Latency (C/L) - 2 or 3

• Data Mask (DQM) for Read / Write Masking

• Programmable Wrap Sequence

– Sequential (B/L = 1/2/4/8/full Page)

– Interleave (B/L = 1/2/4/8)

• Burst Read with Single-bit Write Operation

• Deep Power Down Mode.

• Auto Refresh and Self Refresh

• Special Function Support.

– PASR (Partial Array Self Refresh)

– Auto TCSR (Temperature Compensated Self

Refresh)

• Programmable Driver Strength Control

– Full Strength or 1/2, 1/4 of Full Strength

• 4,096 Refresh Cycles / 64ms (15.625us)

Ordering Information

Part No

EM488M3244LBB-75F

EM488M3244LBB-75FE

Organization

8M X 32

Max. Freq

133MHz @CL3

Package

BGA-90B

Grade

Commercial

Free

Extend temp. Free

* EOREX reserves the right to change products or specification without notice.

May. 2007

1/19

www.eorex.com

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