P4C1023L-25CJI datasheet, PDF - EEWORLD Datasheet

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P4C1023L-25CJI: DescriptionSRAM,; Categorystorage storage; File Size865KB，11 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1023L-25CJI Overview

SRAM,

P4C1023L-25CJI Parametric

Parameter Name	Attribute value
Maker	Pyramid Semiconductor Corporation
package instruction	,
Reach Compliance Code	compliant
ECCN code	EAR99
Date Of Intro	2020-01-13
Memory IC Type	STANDARD SRAM

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P4C1023

HIGH SPEED 128K X 8

SINGLE CHIP ENABLE

FEATURES

Access Times

– 20/25/35/45/55/70 ns

Single 5V±10% Power Supply

Easy Memory Expansion using

and

Inputs

Battery Backup: 2V Data Retention

[P4C1023L only]

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

– 32-Pin 400 or 600 mil Ceramic DIP

– 32-Pin Ceramic SOJ

– 32-Pin Ceramic LCC (400x820 mil) [2-sided]

– 32-Pin Ceramic LCC (450x550 mil)

– 32-Pin Solder Seal Ceramic Flatpack

CMOS STATIC RAM

DESCRIPTION

The P4C1023/L is a 1,048,576-bit high speed CMOS static

RAM organized as 128K x 8. The CMOS memory requires

no clocks or refreshing, and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM operates

from a single 5V±10% tolerance power supply.

Access times of 20 ns to 70 ns are available. CMOS is

utlilized to reduce power consumption to a low level.

The P4C1023/L device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are specified on address pins A

to A

. Reading

is accomplished by device selection (CE low) and output

enabling (OE) while write enable (WE) remains HIGH. By

presenting the address under these conditions, the data in

the addressed memory location is presented on the data

input/output pins. The input/output pins stay in the HIGH

Z state when either

is HIGH or

is LOW. The low

power version offers 2V data retention mode.

The P4C1023/L is packaged in a 32-pin 400 or 600 mil

ceramic DIP and in a 32-pin ceramic SOJ.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (C10, C11), CERAMIC SOJ (CJ1),

SOLDER SEAL FLATPACK (FS-3), LCC (L1)

LCC (L6)

Document #

SRAM141

REV 01

Revised Dec 2019

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