CY7C1511KV18, CY7C1526KV18
CY7C1513KV18, CY7C1515KV18
72-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Features
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Configurations
CY7C1511KV18 – 8M x 8
CY7C1526KV18 – 8M x 9
CY7C1513KV18 – 4M x 18
CY7C1515KV18 – 2M x 36
Separate Independent Read and Write Data Ports
❐
Supports concurrent transactions
333 MHz Clock for High Bandwidth
4-word Burst for Reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 666 MHz) at 333 MHz
Two Input Clocks (K and K) for precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
Separate Port Selects for Depth Expansion
Synchronous Internally Self-timed Writes
QDR™-II operates with 1.5 Cycle Read Latency when DOFF
is asserted HIGH
Operates similar to QDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
Available in x8, x9, x18, and x36 Configurations
Full Data Coherency, providing Most Current Data
Core V
DD
= 1.8V (±0.1V); IO V
DDQ
= 1.4V to V
DD
❐
Supports both 1.5V and 1.8V IO supply
Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable Drive HSTL Output Buffers
JTAG 1149.1 Compatible Test Access Port
Phase Locked Loop (PLL) for Accurate Data Placement
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Functional Description
The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and
CY7C1515KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II architecture has
separate data inputs and data outputs to completely eliminate
the need to “turnaround” the data bus that exists with common
IO devices. Each port can be accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR-II read and write ports are independent of one
another. To maximize data throughput, both read and write ports
are equipped with DDR interfaces. Each address location is
associated with four 8-bit words (CY7C1511KV18), 9-bit words
(CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit
words (CY7C1515KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
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Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
333 MHz
333
600
600
620
850
300 MHz
300
560
560
570
790
250 MHz
250
490
490
500
680
200 MHz
200
430
430
440
580
167 MHz
167
380
380
390
510
Unit
MHz
mA
Cypress Semiconductor Corporation
Document Number: 001-00435 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 30, 2009
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