EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

SK050M2200B3SQ1840

Description
Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 50V, 20% +Tol, 20% -Tol, 2200uF, Through Hole Mount, RADIAL LEADED, ROHS COMPLIANT
CategoryPassive components    capacitor   
File Size66KB,4 Pages
ManufacturerYAGEO
Websitehttp://www.yageo.com/
Environmental Compliance  
Download Datasheet Parametric View All

SK050M2200B3SQ1840 Overview

Aluminum Electrolytic Capacitor, Polarized, Aluminum (wet), 50V, 20% +Tol, 20% -Tol, 2200uF, Through Hole Mount, RADIAL LEADED, ROHS COMPLIANT

SK050M2200B3SQ1840 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerYAGEO
package instruction,
Reach Compliance Codecompli
ECCN codeEAR99
capacitance2200 µF
Capacitor typeALUMINUM ELECTROLYTIC CAPACITOR
dielectric materialsALUMINUM (WET)
leakage current3.3 mA
Manufacturer's serial numberSA
Installation featuresTHROUGH HOLE MOUNT
negative tolerance20%
Number of terminals2
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
Package shapeCYLINDRICAL PACKAGE
method of packingBULK
polarityPOLARIZED
positive tolerance20%
Rated (DC) voltage (URdc)50 V
ripple current1250 mA
surface mountNO
Delta tangent0.12
Terminal shapeWIRE
Common power symbols and their meanings
Power symbols, are you still confused? Commonly used power symbols are attached! In circuit design, there are always various power symbols, which often confuse people. Today, the editor has sorted out...
成都亿佰特 Switching Power Supply Study Group
EEWORLD University - Teach you how to learn LittleVGL
Teach you how to learn LittleVGL step by step : https://training.eeworld.com.cn/course/5682LittlevGL is a free and open source graphics library that provides everything you need to create embedded GUI...
桂花蒸 MCU
Altera SoC Architecture Excerpt - Altera SoC FPGA Adaptive Debug.pdf
Altera SoC Architecture Excerpt - Altera SoC FPGA Adaptive Debug...
雷北城 FPGA/CPLD
5. Common Emitter Amplifier Circuit
1. The structure of the triode, the relationship between the currents of each pole of the triode, the characteristic curve, and the amplification conditions. 2. The role of components, the purpose of ...
wang27349715 Analog electronics
CPLD technology and its application.pdf
CPLD technology and its application.pdf...
zxopenljx EE_FPGA Learning Park
FPGA Design and Implementation of HDLC Control Protocol.pdf
FPGA Design and Implementation of HDLC Control Protocol.pdfClear Format...
zxopenljx EE_FPGA Learning Park

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号