A3PE1500-2PQG484YES datasheet, PDF

Datasheet> All Categories > semiconductor> Programmable logic devices> A3PE1500-2PQG484YES

A3PE1500-2PQG484YES: DescriptionIC,FPGA,38400-CELL,CMOS,BGA,484PIN,PLASTIC; Categorysemiconductor Programmable logic devices; File Size8MB，162 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com

Download Datasheet Parametric View All

A3PE1500-2PQG484YES Overview

IC,FPGA,38400-CELL,CMOS,BGA,484PIN,PLASTIC

A3PE1500-2PQG484YES Parametric

Parameter Name	Attribute value
Number of terminals	484
Minimum operating temperature	0.0 Cel
Maximum operating temperature	70 Cel
state	Active
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
clock_frequency_max	350 MHz
jesd_30_code	S-PBGA-B484
Number of inputs	280
umber_of_logic_cells	38400
Number of outputs	280
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
ckage_equivalence_code	BGA484,22X22,40
packaging shape	SQUARE
Package Size	GRID ARRAY
wer_supplies	1.5/3.3
qualification_status	COMMERCIAL
sub_category	Field Programmable Gate Arrays
surface mount	YES
Craftsmanship	CMOS
Temperature level	Commercial
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM

Preview

Download Datasheet

View All

Revision 13

ProASIC3E Flash Family FPGAs

with Optional Soft ARM Support

Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Pro (Professional) I/O

•

700 Mbps DDR, LVDS-Capable I/Os

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay

Schmitt Trigger Option on Single-Ended Inputs

Weak Pull-Up/-Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the ProASIC

3E Family

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Instant On Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

• FlashLock

Designed to Secure FPGA Contents

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay Capabilities

and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous Operation

up to 350 MHz

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

High-Performance Routing Hierarchy

•

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

Enhanced High-Speed, Very-Long-Line Network

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

ARM

Processor Support in ProASIC3E FPGAs

Table 1-1 • ProASIC3E Product Family

ProASIC3E Devices

Cortex-M1 Devices

System Gates

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Kbits

Secure (AES) ISP

CCCs with Integrated

VersaNet

Globals

I/O Banks

Maximum User I/Os

Package Pins

PQFP

FBGA

PLLs

600,000

13,824

108

Yes

270

PQ208

FG256, FG484

A3PE600

A3PE1500

M1A3PE1500

1,500,000

38,400

270

Yes

444

PQ208

FG484, FG676

A3PE3000

M1A3PE3000

3,000,000

75,264

504

112

Yes

620

PQ208

FG324

FG484, FG896

Notes:

1. Refer to the

Cortex-M1

product brief for more information.

2. The PQ208 package supports six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the

ProASIC3 Flash Family FPGAs

datasheet.

January 2013

ProASIC3E Flash Family FPGAs

Table of Contents

ProASIC3E Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3E DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-3

3-4

Package Pin Assignments

PQ208

FG256

FG324

FG484

FG676

FG896

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

R ev i si o n 1 3

Recommended Resources

Special integrated amplifier for headphone amplifier LM4880-02

MC33466 series buck converter circuit diagram

Transistor driven TTL interface circuit

Air conditioner humidity control application circuit

Common base quartz frequency controlled capacitor feedback oscillator

845ddr computer motherboard circuit diagram_35

Power Amplifier Modules and Their Role in 5G Designs: 5G is one of the most important and powerful technologies ever introduced to the wireless communications market. With significant improvements in data rates, latency, and capacity over 4G, 5G is expec...; btty038 RF/Wirelessly

【Renesas CPK-RA2L1 Development Board】Review - 3: FSP 3.5: [i=s]This post was last edited by MianQi on 2022-11-21 20:31[/i]RT-Thread clearly states in the Renesas RA2L1 Development Practice Guide : Please use version v3.5.0, which can be downloaded from githu...; MianQi Renesas Electronics MCUs

Sipeed GW2A FPGA Development Board Unboxing: [i=s]This post was last edited by WSir14138 on 2022-11-21 22:29[/i]1 Unboxing The Gaoyun GW2A development board that I have been looking forward to for a long time has finally arrived. Without further...; WSir14138 Domestic Chip Exchange

As the industry continues to move toward unified IoT standards: As the industry continues to move toward unified IoT standards, we will continue to support smart home interoperability. Here’s more information about our commitment to supporting Matter:...; btty038 RF/Wirelessly

Matter Conference Highlights: [i=s]This post was last edited by btty038 on 2022-11-21 23:12[/i]Highlight reel of the Matter Media Launch Event at Capital C in Amsterdam....; btty038 RF/Wirelessly

[Sipeed GW2A FPGA development board]—— Unboxing and core board hardware analysis: 1. Unboxing photos2. Core board design2.1. Core board DDR3-204P gold finger appearance Core board DDR3-SODIMM-204P gold finger memory stick appearance design.2.2. DDR3 Memory DesignDDR3: 1Gbit/128MByt...; mars4zhu Domestic Chip Exchange

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components