HY29F002BP-70 datasheet, PDF - EEWORLD Datasheet

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HY29F002BP-70: DescriptionFlash, 256KX16, 70ns, PDIP32, PLASTIC, DIP-32; Categorystorage storage; File Size457KB，40 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY29F002BP-70 Overview

Flash, 256KX16, 70ns, PDIP32, PLASTIC, DIP-32

HY29F002BP-70 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	DIP
package instruction	DIP, DIP32,.6
Contacts	32
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	70 ns
Other features	MINIMUM 100000 PROGRAM/ERASE CYCLES
startup block	BOTTOM
command user interface	YES
Data polling	YES
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDIP-T32
JESD-609 code	e0
length	42.164 mm
memory density	4194304 bi
Memory IC Type	FLASH
memory width	16
Number of functions	1
Number of departments/size	1,2,1,3
Number of terminals	32
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX16
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	5.715 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	15.24 mm

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HY29F002

2 Megabit (256K x 16), 5 Volt-only, Flash Memory

KEY FEATURES

5 Volt Read, Program, and Erase

– Minimizes system-level power requirements

High Performance

– Access times as fast as 45 ns

Low Power Consumption

– 20 mA typical active read current

– 30 mA typical program/erase current

– 1 µA typical CMOS standby current

Compatible with JEDEC Standards

– Package, pinout and command-set

compatible with the single-supply Flash

device standard

– Provides superior inadvertent write

protection

Sector Erase Architecture

– Boot sector architecture with top and

bottom boot block options available

– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte

and three 64K byte sectors

– A command can erase any combination of

sectors

– Supports full chip erase

Erase Suspend/Resume

– Temporarily suspends a sector erase

operation to allow data to be read from, or

programmed into, any sector not being

erased

GENERAL DESCRIPTION

The HY29F002 is an 2 Megabit, 5 volt-only CMOS

Flash memory organized as 262,144 (256K) bytes.

The device is offered in industry-standard 32-pin

PDIP, TSOP and PLCC packages.

The HY29F002 can be programmed and erased

in-system with a single 5-volt V

supply. Inter-

nally generated and regulated voltages are pro-

vided for program and erase operations, so that

the device does not require a high voltage power

supply to perform those functions. The device can

also be programmed in standard EPROM pro-

grammers. Access times as fast as 55ns over the

full operating voltage range of 5.0 volts ± 10% are

offered for timing compatibility with the zero wait

state requirements of high speed microprocessors.

A 45ns version operating over 5.0 volts ± 5% is

also available. To eliminate bus contention, the

A[17:0]

RESET#

CE#

OE#

WE#

DQ[7:0]

Sector Protection

– Any combination of sectors may be

locked to prevent program or erase

operations within those sectors

Temporary Sector Unprotect

– Allows changes in locked sectors

(requires high voltage on RESET# pin)

Internal Erase Algorithm

– Automatically erases a sector, any

combination of sectors, or the entire chip

Internal Programming Algorithm

– Automatically programs and verifies data

at a specified address

Fast Program and Erase Times

– Byte programming time: 7 µs typical

– Sector erase time: 1.0 sec typical

– Chip erase time: 7 sec typical

Data# Polling and Toggle Status Bits

– Provide software confirmation of

completion of program or erase

operations

Minimum 100,000 Program/Erase Cycles

Space Efficient Packaging

– Available in industry-standard 32-pin

PDIP, TSOP and PLCC packages

LOGIC DIAGRAM

Preliminary

Revision 4, January 2000

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