UPD44324182BF5-E40Y-FQ1 datasheet, PDF

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UPD44324182BF5-E40Y-FQ1: Description2MX18 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165; Categorystorage storage; File Size482KB，37 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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UPD44324182BF5-E40Y-FQ1 Overview

2MX18 DDR SRAM, 0.45ns, PBGA165, 15 X 17 MM, PLASTIC, BGA-165

UPD44324182BF5-E40Y-FQ1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Renesas Electronics Corporation
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknow
ECCN code	3A991
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	37748736 bi
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.46 mm
Maximum standby current	0.5 A
Minimum standby current	1.4 V
Maximum slew rate	0.56 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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Datasheet

PD44324092B

PD44324182B

PD44324362B

36M-BIT DDR II SRAM

2-WORD BURST OPERATION

Description

The

PD44324092B is a 4,194,304-word by 9-bit, the

PD44324182B is a 2,097,152-word by 18-bit and the

PD44324362B is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44324092B,

PD44324182B and

PD44324362B integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the

positive edge of K and K#. These products are suitable for application which require synchronous operation,

high speed, low voltage, high density and wide bit configuration.

These products are packaged in 165-pin PLASTIC BGA.

R10DS0036EJ0200

Rev.2.00

August 2, 2011

Features

•

1.8

0.1 V power supply

•

165-pin PLASTIC BGA (15 x 17)

•

HSTL interface

•

PLL circuitry for wide output data valid window and future frequency scaling

•

Pipelined double data rate operation

•

Common data input/output bus

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and K#) for precise DDR timing at clock rising edges only

•

Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability. Normal operation is restored in 20

s after clock is resumed.

•

User programmable impedance output (35 to 70

Ω)

•

Fast clock cycle time : 3.3 ns (300 MHz), 3.5ns (287MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

•

Simple control logic for easy depth expansion

•

JTAG 1149.1 compatible test access port

R10DS0036EJ0100 Rev.2.00

August 2, 2011

Page 1 of 36

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