256K x 8
BOOT BLOCK FLASH MEMORY
FLASH MEMORY
FEATURES
• Five erase blocks:
16KB boot block (protected)
Two 8KB parameter blocks
Two main memory blocks
• SmartVoltage Technology (SVT):
3.3V
±0.3V
or 5V
±10%
V
CC
5V
±10%
or 12V
±5%
V
PP
• Address access times:
60ns, 80ns at 5V V
CC
90ns, 110ns at 3.3V V
CC
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
MT28F002B1
S
MART
V
OLTAGE
PIN ASSIGNMENT (Top View)
40-Pin TSOP Type I
(C-2)
OPTIONS
• Timing (5V V
CC
/3.3V V
CC
)
60ns/90ns access
80ns/110ns access
• Boot Block Starting Address
Top (3FFFFH)
Bottom (00000H)
MARKING
-6
-8
T
B
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
V
PP
WP#
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
NC
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
• Package
Plastic 40-pin TSOP Type 1 (10mm x 20mm) VG
• Part Number Example: MT28F002B1VG-8 T
GENERAL DESCRIPTION
The MT28F002B1 is a nonvolatile, electrically block-
erasable (flash), programmable read-only memory con-
taining 2,097,152 bits organized as 262,144 words by 8 bits.
SmartVoltage Technology (SVT) provides industry-
standard, multi- or single-voltage, dual-supply operation.
Writing or erasing the device is done with either a 5V or 12V
V
PP
voltage, while all operations are performed with a 3.3V
or 5V V
CC
. It is fabricated with Micron’s advanced CMOS
floating-gate process.
The MT28F002B1 is organized into five separately erasable
blocks. To ensure that critical firmware is protected from
accidental erasure or overwrite, the MT28F002B1 features a
hardware-protected boot block. Writing or erasing the boot
256K x 8 Boot Block Flash Memory
F18.p65 – Rev. 2/99
block requires either applying a super-voltage to the RP#
pin or driving WP# HIGH in addition to executing the
normal WRITE or ERASE sequences. This block may be
used to store code implemented in low-level system
recovery. The remaining blocks vary in density and are
written and erased with no additional security measures.
The byte address is issued to read the memory array with
CE# and OE# LOW and WE# HIGH. Valid data is output
until the next address is issued, or CE# or OE# goes HIGH.
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html)
for the latest full-length data
sheet.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
256K x 8
BOOT BLOCK FLASH MEMORY
PIN DESCRIPTIONS
TSOP PIN
NUMBERS
9
SYMBOL
WE#
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# = LOW,
the cycle is either a WRITE to the command execution logic (CEL) or to the
memory array.
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
Write Protect: Unlocks the boot block when HIGH if V
PP
=
V
PPH
1
(5V) or
V
PPH
2
(12V) and RP# = V
IH
during a WRITE or ERASE. Does not affect
WRITE or ERASE operation on other blocks.
Reset/Power-Down: When LOW, RP# clears the status register, sets the
internal state machine (ISM) to the array read mode and places the device
in deep power-down mode. All inputs, including CE#, are “Don’t Care,” and
all outputs are High-Z. RP# unlocks the boot block and overrides the
condition of WP# when at V
HH
(12V), and must be held at V
IH
during all
other modes of operation.
Output Enable: Enables data output buffers when LOW. When OE# is
HIGH, the output buffers are disabled.
Address Inputs: Select a unique byte out of the 262,144 available.
22
12
CE#
WP#
Input
Input
10
RP#
Input
24
21, 20, 19, 18,
17, 16, 15, 14,
8, 7, 36, 6, 5,
4, 3, 2, 1, 40
25, 26, 27, 28,
32, 33, 34, 35
13, 29, 37, 38
11
OE#
A0-A17
Input
Input
DQ0-DQ7
NC
V
PP
Input/
Output
–
Supply
Data I/Os: Data output pins during any READ operation or data input pins
during a WRITE. These pins are used to input commands to the CEL.
No Connect: These pins may be driven or left unconnected.
Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until
completion of the WRITE or ERASE, V
PP
must be at V
PPH
1
(5V) or V
PPH
2
(12V). V
PP
= “Don’t Care” during all other operations.
Power Supply: +5V
±10%
or +3.3V
±0.3V.
Ground.
30, 31
23, 39
V
CC
V
SS
Supply
Supply
256K x 8 Boot Block Flash Memory
F18.p65 – Rev. 2/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
256K x 8
BOOT BLOCK FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F002B1 flash memory incorporates a number
of features to make it ideally suited for system firmware.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting data
stored in other blocks. These memory blocks are read,
written and erased with commands to the command execu-
tion logic (CEL). The CEL controls the operation of the
internal state machine (ISM), which completely controls all
WRITE, BLOCK ERASE and VERIFY operations. The
ISM protects each memory location from over-erasure and
optimizes each memory location for maximum data reten-
tion. In addition, the ISM greatly simplifies the control
necessary for writing the device in-system or in an external
programmer.
The Functional Description provides detailed informa-
tion on the operation of the MT28F002B1 and is organized
into these sections:
•
•
•
•
•
•
•
•
•
•
•
Overview
Memory Architecture
Output (READ) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
WRITE/ERASE Cycle Endurance
Power Usage
Power-Up
blocks require only the V
PP
voltage be present on the V
PP
pin
before writing or erasing.
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or written
only when the RP# pin is taken to V
HH
or when the WP# pin
is brought HIGH. This provides additional security for the
core firmware during in-system firmware updates should
an unintentional power fluctuation or system reset occur.
The MT28F002B1 is available in two versions: the
MT28F002B1T addresses the boot block starting from
3FFFFH, and the MT28F002B1B addresses the boot block
starting from 00000H.
INTERNAL STATE MACHINE (ISM)
BLOCK ERASE and WRITE timing are simplified with an
ISM that controls all erase and write algorithms in the
memory array. The ISM ensures protection against over-
erasure and optimizes write margin to each cell.
During WRITE operations, the ISM automatically incre-
ments and monitors WRITE attempts, verifies write margin
on each memory cell and updates the ISM status register.
When BLOCK ERASE is performed, the ISM automatically
overwrites the entire addressed block (eliminates over-
erasure), increments and monitors ERASE attempts, and
sets bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor to
monitor the status of the ISM during WRITE and ERASE
operations. Two bits of the 8-bit status register are set and
cleared entirely by the ISM. These bits indicate whether the
ISM is busy with an ERASE or WRITE task and when an
ERASE has been suspended. Additional error information
is set in three other bits: V
PP
status, write status and erase
status.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the device.
These commands control the operation of the ISM and the
READ path (i.e., memory array, ID register or status regis-
ter). Commands may be issued to the CEL while the ISM is
active. However, there are restrictions on what commands
are allowed in this condition. See the Command Execution
section for more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F002B1 features a very low current, deep power-
down mode. To enter this mode, the RP# pin is taken to V
SS
±0.2V.
In this mode, the current draw is a maximum of
OVERVIEW
S
MART
V
OLTAGE
TECHNOLOGY (SVT)
SmartVoltage Technology allows maximum flexibility
for in-system READ, WRITE and ERASE operations. For
5V-only systems, WRITE and ERASE operations may be
executed with a V
PP
voltage of 5V. If 12V is available in a
system, the highest WRITE and ERASE performance can be
achieved with a V
PP
voltage of 12V. For any operation, V
CC
may be at 3.3V or 5V.
FIVE INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F002B1 is organized into five independently
erasable memory blocks that allow portions of the memory
to be erased without affecting the rest of the memory
data. A special boot block is hardware-protected against
inadvertent erasure or writing by requiring either a super-
voltage on the RP# pin or driving the WP# pin HIGH. One
of these two conditions must exist along with the V
PP
voltage (5V or 12V) on the V
PP
pin before a WRITE or
ERASE will be performed on the boot block. The remaining
256K x 8 Boot Block Flash Memory
F18.p65 – Rev. 2/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999,
Micron Technology, Inc.
Medical Electronics
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