L8C231JI20 datasheet, PDF - EEWORLD Datasheet

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L8C231JI20: DescriptionFIFO, 2KX9, 12ns, Synchronous, CMOS, PQCC32, 0.490 X 0.590 INCH, PLASTIC, MO-052-AE, MS-016-AE, LCC-32; Categorystorage storage; File Size254KB，17 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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L8C231JI20 Overview

FIFO, 2KX9, 12ns, Synchronous, CMOS, PQCC32, 0.490 X 0.590 INCH, PLASTIC, MO-052-AE, MS-016-AE, LCC-32

L8C231JI20 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	LOGIC Devices
Parts packaging code	QFJ
package instruction	QCCJ, LDCC32,.5X.6
Contacts	32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	12 ns
Maximum clock frequency (fCLK)	50 MHz
period time	20 ns
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
memory density	18432 bi
Memory IC Type	OTHER FIFO
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	2048 words
character code	2000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2KX9
Output characteristics	3-STATE
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.556 mm
Maximum slew rate	0.09 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.43 mm

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L8C211/221/231/241

DEVICES INCORPORATED

512/1K/2K/4K x 9-bit Synchronous FIFO

L8C211/221/231/241

DEVICES INCORPORATED

512/1K/2K/4K x 9-bit Synchronous FIFO

DESCRIPTION

The

L8C211, L8C221, L8C231,

and

L8C241

are synchronous dual-port

First-In/First-Out (FIFO) memories.

The FIFO memory products are

organized as:

L8C211 — 512 x 9-bit

L8C221 — 1024 x 9-bit

L8C231 — 2048 x 9-bit

L8C241 — 4096 x 9-bit

The read and write operations are

internally sequential through the use

of ring pointers. No address informa-

tion is required to load and unload

data. Data present at the input port is

written to the FIFO if the Write Clock

is pulsed when the device is enabled

for writing. Data is read from the

FIFO if the Read Clock is pulsed when

the device is enabled for reading.

Multiple FIFOs can be connected

together to expand the word width

and depth.

These FIFOs are designed to have the

fastest data access possible. Even in

lower cycle time applications, faster

access time can eliminate timing

bottlenecks as well as leave enough

margin to allow the use of the devices

without external bus drivers.

FEATURES

First-In/First-Out (FIFO) using

Dual-Port Memory

Write and Read Clocks can be

synchronous or asynchronous

Advanced CMOS Technology

High Speed — to 15 ns Cycle Time

Empty and Full Warning Flags

Programmable Almost-Empty and

Almost-Full Warning Flags

Plug Compatible with IDT722x1

Package Styles Available:

• 32-pin Plastic LCC, J-Lead

L8C211/221/231/241 B

LOCK

IAGRAM

RESET

LOGIC

WEN

WCLK

WRITE

CONTROL

DATA INPUTS

8-0

INPUT

RAM ARRAY

512 x 9-bit

1K x 9-bit

2K x 9-bit

4K x 9-bit

OUTPUT

DATA OUTPUTS

8-0

Each device utilizes a special algo-

rithm that loads and empties data on a

first-in/first-out basis. Full and

Empty Flags are provided to prevent

data overflow and underflow. Pro-

grammable Almost Full and Almost

Empty Flags are provided and may be

programmed to trigger at any position

in the memory array.

OFFSET

FLAG

LOGIC

EF PAE FF PAF

REN

RCLK

WRITE

POINTER

READ

POINTER

READ

CONTROL

FIFO Products

03/04/99–LDS.8C211/21/31/41-C

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