AT49(H)BV/(H)LV01
Features
•
•
•
•
•
•
•
•
•
•
Single Supply Voltage, Range 2.7V to 3.6V
Single Supply for Read and Write
Fast Read Access Time - 55 ns
Internal Program Control and Timer
8K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte By Byte Programming - 30
µs/Byte
typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50
µA
CMOS Standby Current
•
Typical 10,000 Write Cycles
Description
The AT49(H)BV010 and the AT49(H)LV010 are 3-volt-only, 1-megabit Flash memo-
ries organized as 131,072 words of 8 bits each. Manufactured with Atmel’s advanced
nonvolatile CMOS technology, the devices offer access times to 55 ns with power dis-
sipation of just 90 mW over the commercial temperature range. When the devices are
deselected, the CMOS standby current is less than 50
µA.
To allow for simple in-system reprogrammability, the AT49(H)BV/(H)LV010 does not
require high input voltages for programming. Three-volt-only commands determine
the read and programming operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the AT49(H)BV/(H)LV010 is
performed by erasing the entire 1 megabit of memory and then programming on a
byte by byte basis. The typical byte programming time is a fast 30
µs.
The end of a
program cycle can be optionally detected by the DATA polling feature. Once the end
of a byte program cycle has been detected, a new access for a read or program can
begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
(continued)
1-Megabit
(128K x 8)
Single 2.7-volt
Battery-Voltage
™
Flash Memory
AT49BV010
AT49HBV010
AT49LV010
AT49HLV010
Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
TSOP Top View
Type 1
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PLCC Top View
A12
A15
A16
NC
VCC
WE
A17
14
15
16
17
18
19
20
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
0677B-A–9/97
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
1
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
DATA INPUTS/OUTPUTS
I/O0 - I/O7
OE, CE AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(120K BYTES)
OPTIONAL BOOT
BLOCK (8K BYTES)
Y DECODER
ADDRESS
INPUTS
X DECODER
01FFF
00000
Device Operation
READ:
The AT49(H)BV/(H)LV010 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
ERASURE:
Before a byte can be reprogrammed, the 128K
bytes memory array (or 120K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is t
EC
. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
2
BOOT BLOCK PROGRAMMING LOCKOUT:
The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Com-
mand Definitions table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
AT49(H)BV/(H)LV010
AT49(H)BV/(H)LV010
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49(H)BV/(H)LV010 features
DATA polling to indicate the end of a program cycle. Dur-
ing a program cycle an attempted read of the last byte
loaded will result in the complement of the loaded data on
I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin.
DATA polling may begin at any time during the program
cycle.
TOGGLE BIT:
In addition to DATA polling the
AT49(H)BV/(H)LV010 provides another method for deter-
mining the end of a program or erase cycle. During a pro-
gram or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49(H)BV/(H)LV010 in the following ways: (a) V
CC
sense: if V
CC
is below 1.8V (typical), the program function
is inhibited. (b) Program inhibit: holding any one of OE low,
CE high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
INPUT LEVELS:
While operating with a 2.7V to 3.6V
power supply, the address inputs and control inputs
(OE,
CE and WE) may be driven from 0 to 5.5V without
adversely affecting the operation of the device. The I/O
lines can only be driven from 0 to V
CC
+ 0.6V.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
Addr
Read
Chip Erase
Byte
Program
Boot Block
Lockout
(1)
Product ID
Entry
Product ID
Exit
(2)
Product ID
Exit
(2)
Notes:
1
6
4
6
3
3
1
Addr
5555
5555
5555
5555
5555
XXXX
Data
D
OUT
AA
AA
AA
AA
AA
F0
2AAA
2AAA
2AAA
2AAA
2AAA
55
55
55
55
55
5555
5555
5555
5555
5555
80
A0
80
90
F0
5555
Addr
5555
AA
D
IN
AA
2AAA
55
5555
40
2AAA
55
5555
10
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
1. The 8K byte boot sector has the address range 00000H to 01FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ......................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground......................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground................... -0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground......................... -0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3
DC and AC Operating Range
AT49HLV
010-55
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
AT49LV010
AT49BV010
AT49HBV/
HLV010-70
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
AT49HBV/
HLV010-90
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
AT49BV/
LV010-12
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
2.7V to 3.6V
AT49BV010-15
0°C - 70°C
-40°C - 85°C
N/A
2.7V to 3.6V
0°C - 70°C
-40°C - 85°C
3.0V to 3.6V
N/A
Operating Modes
Mode
Read
Program
(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
V
IL
V
IL
V
IH
A1 - A16 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
A1 - A16 = V
IL
, A9 = V
H
,
(3)
A0 = V
IH
Software
(5)
A0 = V
IL
, A1 - A16 = V
IL
A0 = V
IH
, A1 - A16 = V
IL
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
±
0.5V.
4. Manufacturer Code: 1FH, Device Code: 17H.
5. See details under Software Product Identification Entry/Exit.
Manufacturer Code
(4)
Device Code
(4)
Manufacturer Code
(4)
Device Code
(4)
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High Z
Ai
Ai
Ai
X
I/O
D
OUT
D
IN
High Z
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC(1)
V
IL
V
IH
V
OL
V
OH
Note:
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1. In the erase mode, I
CC
is 50 mA.
I
OL
= 2.1 mA
I
OH
= -100
µA;
V
CC
= 3.0V
2.4
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
CE = 2.0V to V
CC
f = 5 MHz; I
OUT
= 0 mA
Min
Max
10
10
50
1
25
0.6
Units
µA
µA
µA
mA
mA
V
V
V
V
4
AT49(H)BV/(H)LV010
AT49(H)BV/(H)LV010
AC Read Characteristics
AT49HLV
010-55
Symbol
t
ACC
t
CE (1)
t
OE (2)
t
DF (3, 4)
t
OH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output
Float
Output Hold from OE,
CE or Address,
whichever occurred first
0
0
Min
Max
AT49HBV/
HLV010-70
Min
Max
AT49HBV/
HLV010-90
Min
Max
AT49BV/
LV010-12
Min
Max
AT49BV010-
15
Min
Max
Units
ns
ns
ns
ns
ns
55
55
30
25
0
0
70
70
35
25
0
0
90
90
40
25
0
0
120
120
50
30
0
0
0
150
150
70
40
AC Read Waveforms
(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
tCE
OE
tACC
OUTPUT
Notes:
tDF
tOH
OUTPUT VALID
HIGH Z
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impace on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs frist (CL - 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
AC
DRIVING
LEVELS
t
R
, t
F
< 5 ns
Output Test Load
55/70 ns
3.0V
1.8K
OUTPUT
PIN
1.3K
30 pF
1.3K
1.8K
OUTPUT
PIN
100 pF
90/120/150 ns
3.0V
2.4V
1.5V
0.4V
AC
MEASUREMENT
LEVEL
Pin Capacitance
(f = 1 MHz, T = 25°C)
(1)
Typ
C
IN
C
OUT
Note:
4
8
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. This parameter is characterized and is not 100% tested.
5
京公网安备 11010802033920号
EEWORLD
