IS66WVE409616BLL-70TLI datasheet, PDF

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IS66WVE409616BLL-70TLI: DescriptionPseudo Static RAM, 4MX16, 70ns, CMOS, PDSO48, TSOP1-48; Categorystorage storage; File Size674KB，30 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS66WVE409616BLL-70TLI Overview

Pseudo Static RAM, 4MX16, 70ns, CMOS, PDSO48, TSOP1-48

IS66WVE409616BLL-70TLI Parametric

Parameter Name	Attribute value
Maker	Integrated Silicon Solution ( ISSI )
package instruction	TSOP1-48
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	70 ns
JESD-30 code	R-PDSO-G48
length	18.4 mm
memory density	67108864 bi
Memory IC Type	PSEUDO STATIC RAM
memory width	16
Number of functions	1
Number of terminals	48
word count	4194304 words
character code	4000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
width	12 mm

IS66WVE409616BLL-70TLI Preview

IS66WVE409616BLL

Advanced Information

3.0V Core Async/Page PSRAM

Overview

The IS66WVE409616BLL is an integrated memory device containing 64Mbit Pseudo Static Random Access

Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several

power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and

Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power

rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core.

Features

Asynchronous and page mode interface

Dual voltage rails for optional performance

VDD 2.7V~3.6V, VDDQ 2.7V~3.6V

Page mode read access

Interpage Read access : 70ns

Intrapage Read access : 20ns

Low Power Consumption

Asynchronous Operation < 30 mA

Intrapage Read < 18mA

Standby < 180 uA (max.)

Deep power-down (DPD) < 3uA (Typ)

Low Power Feature

Temperature Controlled Refresh

Partial Array Refresh

Deep power-down (DPD) mode

Operating temperature Range

Industrial -40°C~85°C

Packages:

48-ball TFBGA, 48-pin TSOP-I

products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services

described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information

and before placing orders for products.

Rev.00B | February 2010

www.issi.com

- SRAM@issi.com

IS66WVE409616BLL

Advanced Information

General Description

PSRAM products are high-speed, CMOS pseudo-static random access memory developed

for low-power, portable applications. The 64Mb DRAM core device is organized

as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory

interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings.

For seamless operation on an asynchronous memory bus, PSRAM products incorporated a

transparent self-refresh mechanism. The hidden refresh requires no additional support

from the system memory controller and has no significant impact on device read/write

performance.

A user-accessible configuration registers (CR) defines how the PSRAM device performs on-

chip refresh and whether page mode read accesses are permitted. This register is

automatically loaded with a default setting during power-up and can be updated at any

time during normal operation.

Special attention has been focused on current consumption during self-refresh. This

product includes two system-accessible mechanisms to minimize refresh current.

Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array

refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the

DRAM array that contains essential data. DPD halts refresh operation altogether and is

used when no vital information is stored in the device. The system-configurable refresh

mechanisms are accessed through the CR.

A0~A21

Address

Decode Logic

4096K X 16

DRAM

Memory Array

Input

/Output

Mux

And

Buffers

Configuration Register

(CR)

CE#

WE#

OE#

LB#

UB#

ZZ#

Control

Logic

DQ0~DQ15

[ Functional Block Diagram]

Rev.00B | February 2010

www.issi.com

- SRAM@issi.com

IS66WVE409616BLL

Advanced Information

48Ball TFBGA Ball Assignment

LB#

DQ8

DQ9

VSSQ

VDDQ

DQ14

DQ15

A18

OE#

UB#

DQ10

DQ11

DQ12

DQ13

A19

A17

A21

A14

A12

A16

A15

A13

A10

CE#

DQ1

DQ3

DQ4

DQ5

WE#

A11

ZZ#

DQ0

DQ2

VDD

VSS

DQ6

DQ7

A20

[Top View]

(Ball Down)

Rev.00B | February 2010

www.issi.com

- SRAM@issi.com

IS66WVE409616BLL

Advanced Information

48-pin TSOP-I (Top View)

DQ11

DQ3

DQ10

DQ2

VSSQ

OE#

VDDQ

DQ9

DQ1

DQ8

DQ0

A10

A11

UB#

A17

A18

A19

CE#

DQ4

DQ12

ZZ#

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15

VSS

VDD

A16

A15

A14

A13

A12

LB#

A21

A20

WE#

Rev.00B | February 2010

www.issi.com

- SRAM@issi.com

IS66WVE409616BLL

Advanced Information

Signal Descriptions

All signals for the device are listed below in Table 1.

Table 1. Signal Descriptions

Symbol

VDD

VDDQ

VSS

VSSQ

DQ0~DQ15

A0~A21

LB#

UB#

CE#

OE#

WE#

ZZ#

Type

Power Supply

Input / Output

Input

Description

Core Power supply (2.7V~3.6V)

I/O Power supply (2.7V~3.6V)

All VSS supply pins must be connected to Ground

All VSSQ supply pins must be connected to Ground

Data Inputs/Outputs (DQ0~DQ15)

Address Input(A0~A21)

Lower Byte select

Upper Byte select

Chip Enable/Select

Output Enable

Write Enable

Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device

can enter one of two low-power modes ( DPD or PAR).

Rev.00B | February 2010

www.issi.com

- SRAM@issi.com

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IS66WVE409616BLL-70TLI Related Products

	IS66WVE409616BLL-70TLI	IS66WVE409616BLL-70BLI
Description	Pseudo Static RAM, 4MX16, 70ns, CMOS, PDSO48, TSOP1-48	Pseudo Static RAM, 4MX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MO-207, TFBGA-48
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
package instruction	TSOP1-48	6 X 8 MM, MO-207, TFBGA-48
Reach Compliance Code	compli	compli
ECCN code	3A991.B.2.A	3A991.B.2.A
Maximum access time	70 ns	70 ns
JESD-30 code	R-PDSO-G48	R-PBGA-B48
length	18.4 mm	8 mm
memory density	67108864 bi	67108864 bi
Memory IC Type	PSEUDO STATIC RAM	PSEUDO STATIC RAM
memory width	16	16
Number of functions	1	1
Number of terminals	48	48
word count	4194304 words	4194304 words
character code	4000000	4000000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	4MX16	4MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP1	TFBGA
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	BALL
Terminal pitch	0.5 mm	0.75 mm
Terminal location	DUAL	BOTTOM
width	12 mm	6 mm

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