INTEGRATED CIRCUITS
DATA SHEET
TDA8784
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
Product specification
Supersedes data of 1998 Aug 05
File under Integrated Circuits, IC02
1999 Sep 21
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
FEATURES
•
Correlated Double Sampling (CDS), AGC, 10-bit ADC
and reference regulator included, adjustable bandwidth
(CDS and AGC)
•
Fully programmable via a 3-wire serial interface
•
Sampling frequency up to 18 MHz
•
AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)
•
CDS programmable bandwidth from 4 to 120 MHz
•
AGC programmable bandwidth from 4 to 54 MHz
•
Standby mode available for each block for power saving
applications (20 mW typical)
•
6 dB fixed gain analog output for analog iris control
•
8-bit and 10-bit DAC included for analog settings
•
Low power consumption of only 483 mW typical
•
5 V operation and 2.5 to 5.25 V operation for the digital
outputs
•
TTL compatible inputs, TTL and CMOS compatible
outputs.
ORDERING INFORMATION
TYPE
NUMBER
TDA8784HL
PACKAGE
NAME
LQFP48
DESCRIPTION
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
APPLICATIONS
•
CCD camera systems.
GENERAL DESCRIPTION
TDA8784
The TDA8784 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit
Analog-to-Digital Converter (ADC) together with its
reference voltage regulator.
The AGC and CDS have a bandwidth circuit controlled by
on-chip DACs via a serial interface.
A 10-bit DAC controls the ADC input clamp level.
An additional 8-bit DAC is provided for additional system
controls; its output voltage range is 1.4 V (p-p) which is
available at pin OFDOUT.
VERSION
SOT313-2
1999 Sep 21
2
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
QUICK REFERENCE DATA
SYMBOL
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ADC
res
V
i(CDS)(p-p)
G
CDS
f
CLK(max)
AGC
dyn
N
tot(rms)
PARAMETER
analog supply voltage
digital supply voltage
digital outputs supply voltage
analog supply current
digital supply current
digital outputs supply current
ADC resolution
CDS input voltage (peak-to-peak value)
CDS output amplifier gain
maximum clock frequency
AGC dynamic range
total output noise from CDS input to
ADC output (RMS value)
equivalent input noise (RMS value)
total power consumption
gain = 4.5 dB;
f
cut(CDS)
= 120 MHz;
f
cut(AGC)
= 40 MHz
gain = 34.5 dB
f
cut(CDS)
= 120 MHz;
f
cut(AGC)
= 54 MHz
f
CLK
= 18 MHz;
C
L
= 20 pF; ramp input
CONDITIONS
MIN.
4.75
4.75
2.5
−
−
−
−
−
−
18
−
−
TYP.
5
5
3
78
18
1
10
400
6
−
30
0.125
TDA8784
MAX.
5.25
5.25
5.25
85
20
−
−
1200
−
−
−
−
UNIT
V
V
V
mA
mA
mA
bits
mV
dB
MHz
dB
LSB
E
in(rms)
P
tot
−
−
125
483
−
550
µV
mW
1999 Sep 21
3
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
BLOCK DIAGRAM
TDA8784
handbook, full pagewidth
IND
INP AGND3 VCCA3 SHD
46
48
45
44
SHP
43
CLPOB CLPDM
1
42
CLK
41
DGND2
40
VCCD2
39
OE
38
VCCO
37
47
36
TRACK-
AND-HOLD
TRACK-
AND-HOLD
CLOCK
GENERATOR
35
OGND
TRACK-
AND-HOLD
8
5
4-BIT DAC
CUT-OFF
CLAMP
ref1
D9
34
CLAMP
33
CPCDS
AGND1
D8
D7
32
D6
31
AMPOUT
AGND4
4
2
6 dB
10-BIT ADC
OUTPUTS
BUFFER
D5
30
TDA8784
7
1
AGC
29
D4
AGCOUT
D3
28
VCCA1
AGND5
ADCIN
Vref
CLPADC
6
9
10
12
11
8-BIT DAC
10-BIT DAC
REGULATOR
SERIAL
INTERFACE
1
4-BIT DAC
CUT-OFF
9-BIT DAC
D2
27
D1
26
25
3
D0
DGND1
OFDOUT
13
DACOUT
14
15
16
17
18
19
23
22
SEN
21
20
24
VCCD1
MGM505
VCCA2
VRB
VRT
AGND6
DEC1
STDBY
SDATA
SCLK
AGND2
Fig.1 Block diagram.
1999 Sep 21
4
Philips Semiconductors
Product specification
18 Msps, 10-bit analog-to-digital
interface for CCD cameras
PINNING
SYMBOL
CLPOB
AGND4
OFDOUT
AMPOUT
AGND1
V
CCA1
AGCOUT
CPCDS
AGND5
ADCIN
CLPADC
V
ref
DACOUT
AGND2
V
CCA2
V
RB
V
RT
DEC1
AGND6
SDATA
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
clamp pulse input at optical black
analog ground 4
analog output of the additional 8-bit control DAC (controlled via the serial interface)
CDS amplifier output (fixed gain = 6 dB)
analog ground 1
analog supply voltage 1
AGC amplifier signal output
clamp storage capacitor pin
analog ground 5
ADC analog signal input from AGCOUT via a short circuit
DESCRIPTION
TDA8784
clamp control input for ADC analog input signal clamp (used with a capacitor from V
ref
to ground)
ADC input clamp reference voltage (normally connected to pin V
RB
or DACOUT, or shorted to
ground via a capacitor)
DAC output for ADC clamp level
analog ground 2
analog supply voltage 2
ADC reference voltage (BOTTOM) code 0
ADC reference voltage (TOP) code 1023
decoupling 1 (decoupled to ground via a capacitor)
analog ground 6
serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode
per block and edge pulse control); see Table 1
serial clock input for the control DACs and their serial interface; see Table 1
enable input for the serial interface shift register (active when SEN = logic 0); see Table 1
standby control pin (active HIGH); all the output bits are logic 0 when standby is enabled
digital supply voltage 1
digital ground 1
ADC digital output 0 (LSB)
ADC digital output 1
ADC digital output 2
ADC digital output 3
ADC digital output 4
ADC digital output 5
ADC digital output 6
ADC digital output 7
ADC digital output 8
ADC digital output 9 (MSB)
digital output ground
digital output supply voltage
SCLK
SEN
STDBY
V
CCD1
DGND1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OGND
V
CCO
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
1999 Sep 21
5
Analog electronics
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