The HM-6617 CMOS PROM is manufactured with all bits
containing a logical zero (output low). Any bit can be pro-
grammed selectively to a logical one (output high) state by
following the procedure shown below. To accomplish this, a
programmer can be built that meets the specifications
shown, or any of the approved commercial programmers
can be used.
Programming Sequence Of Events
1. Apply a voltage of V
CC1
to V
CC
of the PROM.
2. Read all fuse locations to verify that the PROM is blank
(output low).
3. Place the PROM in the initial state for programming: E =
V
IH
, P = V
IH
, G = V
IL
.
4. Apply the correct binary address for the word to be pro-
grammed. No inputs should be left open circuit.
5. After a delay of tD, apply voltage of V
IL
to E (pin 18) to ac-
cess the addressed word.
6. The address may be held through the cycle, but must be
held valid at least for a time equal to tD after the falling
edge of E. None of the inputs should be allowed to float
to an invalid logic level.
7. After a delay of tD, disable the outputs by applying a volt-
age of V
IH
to G (pin 20).
8. After a delay of tD, apply voltage of V
IL
to P (pin 21).
9. After delay of tD, raise V
CC
(pin 24) to VCCPROG with a
rise time of tR. All outputs at V
IH
should track V
CC
with
V
CC
-2.0V to V
CC
+0.3V. This could be accomplished by
pulling outputs at V
IH
to V
CC
through pull-up resistors of
value Rn.
10. After a delay of tD, pull the output which corresponds to
the bit to be programmed to V
IL
. Only one bit should be
programmed at a time.
11. After a delay of tPW, allow the output to be pulled to V
IH
through pull-up resistor Rn.
12. After a delay of tD, reduce V
CC
(pin 24) to V
CC1
with a fall
time of tF. All outputs at V
IH
should track V
CC
with V
CC
2.0V
to V
CC
+0.3V. This could be accomplished by pulling out-
puts at V
IH
to V
CC
through pull-up resistors of value Rn.
13. Apply a voltage of V
IH
to P (pin 21).
14. After a delay of tD, apply a voltage of V
IL
to G (pin 20).
15. After a delay of tD, examine the outputs for correct data. If
any location verifies incorrectly, repeat steps 4 through 14
(attempting to program only those bits in the word which
verified incorrectly) up to a maximum of eight attempts for
a given word. If a word does not program within eight at-
tempts, it should be considered a programming reject.
16. Repeat steps 3 through 15 for all other bits to be pro-
grammed in the PROM.
Post-Programming Verification
17. Place the PROM in the post-programming verification
mode: E = V
IH
, G = V
IL
, P = V
IH
, V
CC
(pin 24) = V
CC1
.
18. Apply the correct binary address of the word to be veri-
fied to the PROM.
19. After a delay of tD, apply a voltage of V
IL
to E (pin 18).
20. After a delay of tD, examine the outputs for correct data.
If any location fails to verify correctly, the PROM should
be considered a programming reject.
21. Repeat steps 17 through 20 for all possible programming
locations
Post-Programming Read
22. Apply a voltage of V
CC2
= 4.0V to V
CC
(pin 24).
23. After a delay of tD, apply a voltage of V
IH
to E (pin 18).
24. Apply the correct binary address of the word to be read.
25. After a delay of TAVEL, apply a voltage of V
IL
to E (pin
18).
26. After a delay of TELQV, examine the outputs for correct
data. If any location fails to verify correctly, the PROM
should be considered a programming reject.
27. Repeat steps 23 through 26 for all address locations.
28. Apply a voltage of V
CC2
= 6.0V to V
CC
(pin 24).
29. Repeat steps 23 through 26 for all address locations.
3
HM-6617
Programming Cycle
PROGRAMMING
V
CC
PROG
V
IH
V
IL
V
IH
V
IL
tD
G
V
CC
PROG
V
IH
V
IL
V
CC
PROG
V
IH
V
IL
V
CC
PROG
V
CC
GND
V
CC
PROG
V
IH
/V
OH
V
IL
/V
OL
tR
tD
VERIFY
A
VALID
tD
VALID
TEHEL
E
tD
P
tD
V
CC
tD
tPW
tD
tF
READ DATA
Q
FIGURE 1. HM-6617 PROGRAMMING CYCLE
A
V
IH
V
IL
TAVEL
VALID
TEHEL
TEHEL
E
V
IH
V
IL
TEHEL
6.0V
5.0V
4.0V
tD
tD
V
CC
0.0V
TELQV
V
OH
V
OL
TELQV
TELQV
Q
READ
READ
READ
FIGURE 2. HM-6617 POST PROGRAMMING VERIFY CYCLE
4
HM-6617
Background Information HM-6617 Programming
Programming Specifications
SYMBOL
V
IL
V
IH
VCCPROG
V
CC1
V
CC2
tD
tR
tF
TEHEL
TAVEL
TELQV
tPW
tIP
IOP
Rn
T
A
NOTES:
1. All inputs must track V
CC
(pin 24) within these limits.
2. VCCPROG must be capable of supplying 500mA.
3. See Steps 22 through 29 of the Programming Algorithm.
4. See Step 11 of the Programming Algorithm.
5. All outputs should be pulled up to V
CC
through a resistor of value Rn.
6. Except during programming (See Programming Cycle Waveforms).
Input “0”
Voltage “1” (Note 6)
Programming V
CC
(Note 2)
Operating V
CC
Special Verify V
CC
(Note 3)
Delay Time
Rise Time
Fall Time
Chip Enable Pulse Width
Address Valid to Chip Enable Low Time
Chip Enable Low to Output Valid Time
Programming Pulse Width (Note 4)
Input Leakage at V
CC
= VCCPROG
Data Output Current at V
CC
= VCCPROG
Output Pull-Up Resistor (Note 5)
Ambient Temperature
PARAMETER
MIN
0.0
VCC-2
12.0
4.5
4.0
1.0
1.0
1.0
50
20
-
90
-10
-
5
-
TYP
0.2
V
CC
12.0
5.5
-
1.0
10.0
10.0
-
-
-
100
+1.0
-5.0
10
25
MAX
0.8
VCC+0.3
12.5
5.5
6.0
-
10.0
10.0
-
-
120
110
10
-10
15
-
UNITS
V
V
V
V
V
µs
µs
µs
ns
ns
ns
µs
µA
mA
kΩ
o
C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
京公网安备 11010802033920号
EEWORLD
