IC62LV25616L
IC62LV25616LL
Document Title
256Kx16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
0B
History
Initial Draft
Draft Date
May 1,2001
Remark
Preliminary
1. Change for t
PWE
: 45 to 40 ns for 55 ns product
August 21,2001
: 60 to 40 ns for 70 ns product
2. Change for V
CC
: 2.2-3.6V to 2.7-3.6V
3.1 Change for I
CC
test conditiomn: V
CC
=Max. to 3V
3.2 Change for I
CC
: 35 to 40mA for 55 ns commercial product
30 to 35mA for 70 ns commercial porduct
25 to 30 mA for 100 ns commercial product
4. Change for I
SB1
test conditions: with
CE
controlled only
5.1 Change for V
DR
Min. : 1.2 to 1.5V
5.2 Change for I
DR
test condition: V
CC
=1.2 to 1.5V
January 29,2002
1.Change for I
CC
: 40 mA to 25 mA for 55 ns
35 mA to 20 mA for 70 ns
30 mA to 15mA for 100 ns
2.Change for I
DR
: 4µA to 5 µA for commercial/LL product
6µA to 9 µA for Industrial/LL Product
October 9,2002
Change for V
OH
: 2.0V to 2.4V
0C
0D
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR013-0D 10/11/2002
1
IC62LV25616L
IC62LV25616LL
256K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access times: 55, 70, 100 ns
•
CMOS low power operation
-- 60 mW (typical) operating
-- 3 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.6V Vcc power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA
DESCRIPTION
The
ICSI
IC62LV25616L and IC62LV25616LL are low-power,
4.194,304 bit static RAMs organized as 262,144 words by 16
bits. They are fabricated using
ICSI
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When
CE
is HIGH (deselected) or both
LB
and
UB
are HIGH,
the device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC62LV25616L and IC62LV25616LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
LPSR013-0D 10/11/2002
IC62LV25616L
IC62LV25616LL
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
2.7V- 3.6V
2.7V - 3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
V
CC
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–40 to +85
–0.3 to +4.0
–65 to +150
1.0
Unit
V
°C
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
(1)
V
IL
(2)
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
I
OH
= –1 mA
I
OL
= 2.1 mA
Min.
2.4
—
2.2
–0.2
–1
–1
Max.
—
0.4
V
CC
+ 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, O
UTPUTS
D
ISABLED
Notes:
1. V
IH
(max.) = V
CC
+2.0V for pulse width less than 10 ns.
2. V
IL
(min.) = –2.0V for pulse width less than 10 ns.
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Circuit Solution Inc.
LPSR013-0D 10/11/2002
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