M7A3P600-FGG144I datasheet, PDF

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M7A3P600-FGG144I: DescriptionField Programmable Gate Array, 600000 Gates, 350MHz, 13824-Cell, CMOS, PBGA144, 1 MM PITCH, GREEN, FBGA-144; CategoryProgrammable logic devices Programmable logic; File Size3MB，246 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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M7A3P600-FGG144I Overview

Field Programmable Gate Array, 600000 Gates, 350MHz, 13824-Cell, CMOS, PBGA144, 1 MM PITCH, GREEN, FBGA-144

M7A3P600-FGG144I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	1 MM PITCH, GREEN, FBGA-144
Reach Compliance Code	compli
maximum clock frequency	350 MHz
JESD-30 code	S-PBGA-B144
JESD-609 code	e1
length	13 mm
Humidity sensitivity level	3
Equivalent number of gates	600000
Number of entries	97
Number of logical units	13824
Output times	97
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	600000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA144,12X12,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	1.8/2.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.55 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	13 mm

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v2.1

ProASIC

3 Flash Family FPGAs

with Optional Soft ARM

Support

Features and Benefits

High Capacity

•

30 k to 1 Million System Gates

Up to 144 kbits of True Dual-Port SRAM

Up to 300 User I/Os

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

Live at Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

1 kbit of FlashROM with Synchronous Interfacing

350 MHz System Performance

3.3 V, 66 MHz 64-Bit PCI (except A3P030)

Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except A3P030 and ARM

enabled ProASIC

3 devices) via JTAG (IEEE 1532–

compliant)

FlashLock

to Secure FPGA Contents

Core Voltage for Low Power

Support for 1.5-V-Only Systems

Low-Impedance Flash Switches

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

Enhanced High-Speed, Very-Long-Line Network

•

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

Advanced I/O

700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—Up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except

A3P030), and LVCMOS 2.5 V / 5.0 V Input

Differential I/O Standards: LVPECL, LVDS, BLVDS, and

M-LVDS (A3P250 and above)

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold Sparing I/Os (A3P030 only)

Programmable Output Slew Rate (except A3P030) and

Drive Strength

Weak Pull-Up/Down

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages Across the ProASIC3 Family

Six CCC Blocks, One with an Integrated PLL

Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback, Multiply/Divide,

Delay Capabilities, and External Feedback

Wide Input Frequency Range (1.5 MHz to 350 MHz)

CoreMP7Sd (with debug) and CoreMP7S (without debug

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,

×4, ×9, and ×18 Organizations Available)

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

CoreMP7Sd (with debug) and CoreMP7S (without

debug)

Reprogrammable Flash Technology

On-Chip User Nonvolatile Memory

High Performance

In-System Programming (ISP) and Security

Clock Conditioning Circuit (CCC) and PLL (except A3P030)

•

Low Power

SRAMs and FIFOs (except A3P030)

High-Performance Routing Hierarchy

Soft ARM7™ Core Support in M7 ProASIC3 Devices

•

Table 1 •

ProASIC3 Product Family

A3P030

A3P060

A3P125

A3P250

M7A3P250

30 k

768

–

QN132

VQ100

60 k

1,536

Yes

QN132

VQ100

TQ144

FG144

125 k

3,072

Yes

133

QN132

VQ100

TQ144

PQ208

FG144

250 k

6,144

Yes

157

QN132

VQ100

PQ208

FG144,

FG256

PQ208

FG144, FG256,

FG484

PQ208

FG144, FG256,

FG484

PQ208

FG144, FG256,

FG484

ProASIC3 Devices

ARM

-Enabled

ProASIC3 Devices

System Gates

VersaTiles (D-flip-flops)

RAM kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Bits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

QFN

VQFP

TQFP

PQFP

FBGA

A3P400

M7A3P400

400 k

9,216

Yes

194

A3P600

M7A3P600

600 k

13,824

108

Yes

235

A3P1000

M7A3P1000

24,576

144

Yes

300

Notes:

1. Refer to the

CoreMP7

datasheet for more information.

2. AES is not available for ARM-enabled ProASIC3 devices.

3. Six chip (main) and three quadrant global networks are available for A3P060 and above.

4. For higher densities and support of additional features, refer to the

ProASIC3E Flash FPGAs

datasheet.

5. The M7A3P250 device does not support this package.

May 2007

See the Actel website for the latest version of the datasheet.

ProASIC3 Flash Family FPGAs

Table of Contents

Introduction and Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

Device Architecture

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52

Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95

Package Pin Assignments

132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44

484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

v2.1

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