Product Brief
Axcelerator Family FPGAs
u e
™
Leading-Edge Performance
•
•
•
•
•
•
•
•
•
350+ MHz System Performance
500+ MHz Internal Performance
High-Performance Embedded FIFOs
700 Mb/s LVDS Capable I/Os
Up to 2 Million Equivalent System Gates
Up to 684 I/Os
Up to 10,752 Dedicated Flip-Flops
Up to 295 kbits Embedded SRAM/FIFO
Manufactured on Advanced 0.15
μm
CMOS Antifuse
Process Technology, 7 Layers of Metal
Single-Chip, Nonvolatile Solution
Up to 100% Resource Utilization with 100% Pin Locking
1.5V Core Voltage for Low Power
Footprint Compatible Packaging
Flexible, Multi-Standard I/Os:
– 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V
PCI, and 3.3V PCI-X
– Differential I/O Standards: LVPECL and LVDS
AX125
125,000
82,000
672
1,344
1,344
4
18,432
4
4
8
8
168
84
504
180
Specifications
•
Features
•
•
•
•
•
•
•
•
•
•
•
Voltage-Referenced I/O Standards: GTL+, HSTL
Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Registered I/Os
– Hot-Swap Compliant I/Os (except PCI)
– Programmable Slew Rate and Drive Strength on
Outputs
– Programmable Delay and Weak Pull-Up/Pull-Down
Circuits on Inputs
Embedded Memory:
– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18, x36 Organizations Available)
– Independent, Width-Configurable Read and Write Ports
– Programmable Embedded FIFO Control Logic
Segmentable Clock Resources
Embedded Phase-Locked Loop:
– 14-200 MHz Input Range
– Frequency Synthesis Capabilities up to 1 GHz
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Actel Silicon Explorer II
Boundary-Scan Testing Compliant with IEEE Standard
1149.1 (JTAG)
FuseLock
TM
Secure Programming Technology
Prevents Reverse Engineering and Design Theft
–
Table 1-1 •
Axcelerator Family Product Profile
Device
Capacity (in Equivalent System Gates)
Typical Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Maximum Flip-Flops
Embedded RAM/FIFO
Number of Core RAM Blocks
Total Bits of Core RAM
Clocks (Segmentable)
Hardwired
Routed
PLLs
I/Os
I/O Banks
Maximum User I/Os
Maximum LVDS Channels
Total I/O Registers
Package
CSP
PQFP
BGA
FBGA
CQFP
CCGA
AX250
250,000
154,000
1,408
2,816
2,816
12
55,296
4
4
8
8
248
124
744
AX500
500,000
286,000
2,688
5,376
5,376
16
73,728
4
4
8
8
336
168
1,008
AX1000
1,000,000
612,000
6,048
12,096
12,096
36
165,888
4
4
8
8
516
258
1,548
AX2000
2,000,000
1,060,000
10,752
21,504
21,504
64
294,912
4
4
8
8
684
342
2,052
208
256, 324
256, 484
208, 352
208
484, 676
208, 352
729
484, 676, 896
352
624
896, 1152
352
624
November 2008
© 2008 Actel Corporation
1
Axcelerator Family FPGAs
Ordering Information
AX1000 _
1
FG
G
896
I
Application
Blank =
Commercial
(0 to +70°
C)
PP = Pre-Production
I = Industrial (-40 to +85°
C)
M = Military (-55 to +125°
C)
B = MIL-STD-883
Class
B
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant Packaging
Package Type
BG = Ball
Grid
Array (1.27mm pitch)
FG = Fine Ball
Grid
Array (1.0mm pitch)
CS
=
Chip Scale
Package (0.8mm pitch)
PQ = Plastic Quad Flat Pack (0.5mm pitch)
CQ
=
Ceramic
Quad Flat Pack (0.5mm pitch)
CG
=
Ceramic Column Grid
Array
Speed Grade
Blank =
Standard Speed
1 = Approximately 15% Faster than
Standard
2 = Approximately 25% Faster than
Standard
Part Number
AX125 = 125,000 Equivalent
System Gates
AX250 = 250,000 Equivalent
System Gates
AX500 = 500,000 Equivalent
System Gates
AX1000 = 1,000,000 Equivalent
System Gates
AX2000 = 2,000,000 Equivalent
System Gates
Device Resources
User I/Os (Including Clock Buffers)
Package
CS180
PQ208
CQ208
FG256
FG324
CQ352
FG484
CG624
FG676
BG729
FG896
FG1152
AX125
98
–
–
138
168
–
–
–
–
–
–
–
AX250
–
115
115
138
–
198
248
–
–
–
–
–
AX500
–
115
115
–
–
198
317
–
336
–
–
–
AX1000
–
–
–
–
–
198
317
418
418
516
516
–
AX2000
–
–
–
–
–
198
–
418
–
–
586
684
Note:
The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint
compatible with one another.
2
P ro du ct B ri e f
Axcelerator Family FPGAs
Temperature Grade Offerings
Package
CS180
PQ208
CQ208
FG256
FG324
CQ352
FG484
CG624
FG676
BG729
FG896
FG1152
Notes:
1.
2.
3.
4.
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883 Class B
AX125
C, I
–
–
C, I
C, I
–
–
–
–
–
–
–
AX250
–
C, I, M
M, B
C, I, M
–
M, B
C, I, M
–
–
–
–
–
AX500
–
C, I, M
M, B
–
–
M, B
C, I, M
–
C, I, M
–
–
–
AX1000
–
–
–
–
–
M, B
C, I, M
M, B
C, I, M
C, I, M
C, I, M
–
AX2000
–
–
–
–
–
M, B
–
M, B
–
–
C, I, M
C, I, M
Speed Grade and Temperature Grade Matrix
Std
C
I
M
B
Notes:
5.
6.
7.
8.
C = Commercial
I = Industrial
M = Military
B = MIL-STD-883 Class B
✓
✓
✓
✓
–1
✓
✓
✓
✓
–2
✓
✓
–
–
Contact your local Actel representative for device availability.
P r o du c t B r i ef
3
Axcelerator Family FPGAs
General Description
Actel’s newest FPGA family, Axcelerator offers high
performance at densities of up to two million equivalent
system gates. Based upon Actel’s new AX architecture,
Axcelerator has several system level features such as
embedded SRAM (with complete FIFO control logic),
PLLs, Segmentable Clocks, and chip-wide highway
routing.
flop and the Combinatorial Cell (C-cell), containing a
four-input MUX with control and carry-chain logic.
Two C-cells and a single R-cell form a Cluster, and two
Clusters comprise a SuperCluster. SuperClusters are
organized into Core Tiles, which are combined to
generate each device (please refer to the Axcelerator
Family FPGAs data sheet for more information).
Additionally, each SuperCluster contains an independent
Buffer Module. Buffer Modules support automatic buffer
insertion for high-fanout nets by the place-and-route
tool, providing better overall system delays while
improving logic utilization.
The AX architecture is fully fracturable, meaning that if
one or more of the logic modules in a SuperCluster are
used by a particular signal path, the other logic modules
are still available for use by other paths.
Device Architecture
Actel's AX architecture, derived from the highly
successful SX-A sea-of-modules architecture, has been
designed for high performance and total logic module
utilization (Figure
1).
There are two base logic modules:
the Register Cell (R-cell), containing a full-featured flip-
SuperCluster
C
C
R
TX
RX
TX
RX
B
TX
RX
TX
RX
C
C
R
RAMC
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4k
RAM/
FIFO
4k
RAM/
FIFO
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
HD
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
RAMC
Chip Layout
4k
RAM/
FIFO
4k
RAM/
FIFO
SC
SC
Core
SC
Tile
I/O Structure
See Figure 7
Figure 1 •
AX Device SuperCluster
4
P ro du ct B ri e f
Axcelerator Family FPGAs
Embedded Memory
The embedded, variable-aspect-ratio SRAM blocks have
separate read and write ports that can be configured
with different bit widths on each port. Available memory
configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or
4kx1 bit. Additionally, every SRAM block has an
embedded FIFO control unit. The control unit allows the
SRAM block to be configured as a synchronous FIFO, with
programmable
DEPTH
and
programmable
ALMOSTEMPTY and ALMOST-FULL flags in addition to
the normal FULL and EMPTY flags.
The embedded FIFO control unit also contains the
counters necessary for the generation of the read and
write address pointers as well as metastable control
circuitry to prevent erroneous operation. The metastable
control circuitry, when combined with the FIFO’s ability
for asynchronous reads and writes, enables these
embedded structures to be used to cross both clock and
phase domains.
Global Resources
Each family member has three types of global signals
available to the designer: HCLK, CLK, and GCLR/GPSET.
There are four hardwired clocks (HCLKs) per device,
which can directly drive the clock input of an R-Cell. Each
of the four routed clocks (CLKs) can drive the clock, clear,
preset, or enable pin of an R-cell or any input of a C-cell.
Global clear (GCLR) and global preset (GPSET) can drive
the clear and preset inputs of each R-Cell as well as each
I/O Register on a chip-wide basis at power up.
Each HCLK and CLK has an associated analog PLL for a
total of eight per chip. Each embedded PLL can be used
for clock delay minimization, clock delay adjustment, or
clock frequency synthesis. The PLL can operate with
input frequencies ranging from 14 MHz to 200 MHz and
can generate output frequencies between 20 MHz and
1 GHz. The clock can be either divided or multiplied by
up to a factor of 64, or multiply and divide settings can
be in any combination as long as the resulting clock does
not exceed the absolute maximum output value (1 GHz).
Additionally, the PLL can be used to introduce either a
positive or a negative clock delay of up to 3.75 ns in 250
ps increments. The reference clock needed to drive the
PLL can be derived from three sources: an external input
pad (configured as either single-ended or differential),
internal logic, or from the output of an adjacent PLL.
I/Os
The Axcelerator family of FPGAs also features a flexible I/O
structure, supporting a range of mixed voltages with its
bank-selectable I/O: 1.5V, 1.8V, 2.5V and 3.3V. In total,
Axcelerator FPGAs support at least 14 different I/O
standards (single-ended, differential, voltage-referenced).
The I/Os are organized into banks, with eight banks per
device (two per side). All I/O options are 3.3V tolerant;
the 3.3V PCI option is 5V tolerant with the aid of an
external resistor. All I/O options except 3.3V PCI are hot-
insertion capable.
Each I/O has an input, output, and enable register.
Summary
Actel’s Axcelerator family of FPGAs expands the
successful SX-A architecture, adding embedded RAM/
FIFOs, PLLs, and high-speed I/Os. The Axcelerator family
also provides the designer with high-performance at
high-gate counts with high device utilization even with
fixed pins. With the support of a suite of robust software
tools, design engineers can incorporate high gate counts
and fixed pins into an Axcelerator design yet still achieve
high performance and efficient device utilization.
Routing
Tying all of the device resources together is the AX
hierarchical routing structure, enabling the Axcelerator
family’s high performance and utilization. At the lowest
level in and SuperClusters below, there are three routing
structures:
DirectConnects,
FastConnects,
and
CarryConnects. DirectConnects provide very high
performance routing inside the SuperCluster, while
FastConnects provide high performance routing inside
the SuperCluster and to the below SuperCluster.
CarryConnect routing is used between SuperClusters
when building arithmetic functions. The core tile routing
is at the next level. Both vertical and horizontal tracks
run across a row or column of SuperClusters within a
core tile respectively. At the chip level, routing highways
extend across the full length of the device, both north-
to- south and east-to-west.
P r o du c t B r i ef
5
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